JESD204B Converters Simplify FPGA And ASIC Interfacing

Nov. 20, 2012
JESD204B SERDES Tx and Rx facilitates connecting multiple high-speed, high-res data converters to FPGAs or ASICs. story describes how it does that with reduced pin-count and low, deterministic, latency.

It isn’t unusual for an analog-to-digital converter (ADC) to be Electronic Design’s Best Analog product of the year, particularly when its performance characteristics are remarkable. Yet in this case, it’s Analog Devices’ deep involvement with the design community, as much as the product’s performance characteristics, that deserve attention.

On October 8, ADI announced sampling of the first four ADCs in its JESD204B-compatible High-Speed Data Converter-to-FPGA Interconnect Design Environment products. The ADCs are representative of a new era in which products evolve within a community that works to solve an over-reaching problem. Today, standards drive semiconductor innovation.

For example, ADI has worked with high-performance FPGA suppliers such as Xilinx Inc. that have incorporated on-chip JESD204B serializer-deserializer (SERDES) ports into their latest products to provide end-to-end seamless connectivity for the analog signal chain. For the product designer, this means faster turns on new product designs. In addition, ADI worked with Tektronix on testing standards for both ends of the interface. Of course, there are also demo boards and reference designs, along with ADI’s “Circuits from the Lab.”

Nor are these narrowly focused products. According to ADI, the JEDEC JESD204B standard is broadly important because the technology it embodies is bound to replace the low-voltage differential signaling (LVDS) that is common today, having all but supplanted CMOS as the high-speed, high-resolution converter interface technology of choice for high-performance applications.

JESD204’s Evolution

The original version of JESD204 described a multi-gigabit serial data link between converter(s) and a receiver, such as an FPGA or ASIC. It was developed because, as the resolution and speed of converters continued to increase, the demand for a more efficient interface between multiple converters and FPGAs and ASICs had grown.

In the years since the initial release, two drivers have made revisions necessary—faster converter sampling rates and higher converter resolutions—making converter package footprints awkward.  Both issues were addressed by increasing the carrying capacity of the lanes between converters and FPGAs, which required a synchronization method to ensure deterministic latency (see the figure).

1. JESD204B multi-lane serial interfacing makes it possible to convert many high-speed, high-resolution ADCs and DACs an FPGA or ASIC with a small number of copper conductors. This makes for smaller device footprints and simpler routing on the circuit board.

The baseline JESD204 standard of 2006 was followed by a revision two years later. The latest 2011 JESD204 “B” version tops its predecessor in terms of allowable converter speed, size, and cost. Like the earlier versions, it defines standards for ADCs, digital-to analog-converters (DACs), and FPGAs, and it’s being rapidly adopted.

Original PHY Layer

In the first release of the standard, the data link was a single serial lane between one or more converters and a receiver. The physical layer (PHY) consisted of a differential pair of current mode logic (CML) drivers and receivers. A frame clock was routed to both. On the original lanes, data rates between 312.5 Mbits/s and 3.125 Gbits/s were allowed, and the permissible load impedance was 100 Ω ±20%. The nominal differential voltage level was 800 mV p-p, and common mode voltage could range from 0.72 to 1.23 V. The link utilized 8- or 10-bit encoding with an embedded clock.

Latency Is The Key

As designers became experienced with the original standard and tried to apply it to systems with more and faster converters, it was clear that additional lanes were needed, along with faster signal rates and ways to handle higher-resolution converters. The 2008 Rev-A version of JESD204 added support for multiple aligned serial lanes with multiple converters. Lane data rates, the frame clock, and the electrical interface stayed the same. 

In particular, as in the original standard, the latency in any lane was undefined. (ADC latency is the number of clock cycles between the instant of the sampling edge of the input signal and the time that its digital representation is present at the converter’s outputs. In a DAC, it’s the number of clock cycles between the time the digital signal is clocked into the DAC and the time the analog output begins changing.)  

First Revision

Rev A was welcomed, but converter speed and resolutions still kept getting better. More had to be done. In response, JESD204B was released in July 2011. Permissible data rates increased to 12.5 Gbits/s, and a way to use the device clock instead of the frame clock as the main clock source was included.

Most importantly, JESD204B now provided a way to guarantee that latency is repeatable and deterministic with every actuation and across link re-synchronization events. Synchronization may happen in different ways. In one, the initial lane alignment sequence in all the converters occurs simultaneously across all lanes at a time established by a new input signal, “SYNC~.”   

Another way to provide deterministic latency employs a second newly defined signal, SYSREF. It acts as a master timing reference and aligns all the internal dividers from device clocks and local multi-frame clocks in each transmitter and receiver. 

For flexibility, JESD204B introduces three device sub-classes. Sub-class 0 does not support deterministic latency. Sub-class 1, for use up to 500 Mbytes/s, employs SYSREF. Sub-class 2, for use above 500 Mbytes/s, employs SYNC~. In addition to providing for deterministic latency, the JESD204B version increases the supported lane data rates to 12.5 Gbits/s and divides devices into three different speed grades.

The first aligns with the lane data rates from the original JESD204 and the JESD204A versions of the standard and defines the electrical interface for lane data rates up to 3.125 Gbits/s. The second defines the electrical interface for lane data rates up to 6.375 Gbit/s. This speed grade lowers the minimum differential voltage level to 400 mV p-p, down from 500 mV p-p for the first speed grade. The third defines details of the electrical interface for lane data rates up to 12.5 Gbit/s. It lowers the minimum differential voltage level required for the electrical interface to 360 mV p-p. To accommodate lane data rate increases, the standard lowers the minimum required differential voltage level.

For flexibility, the new standards allow a device clock instead of a frame clock. Each converter and receiver is run off a common clock generator circuit. This is going to require the relationship between the frame clock and device clock to be specified in each device’s datasheet.

Product Lineup

ADI’s initial products for JESD204B applications include four converters: the AD9250 14-bit, 170/250-Msample/s, dual ADC; the AD9644 14-bit, 80/155-Msample/s, 1.8-V dual, serial-output ADC; the AD9641 14-bit, 80/155-Msample/s, 1.8-V, single serial-output ADC; and the AD9639  quad 12-bit, 170/210-Msample/s, serial-output 1.8-V ADC.

The AD9250 targets applications such as software-defined radios and medical ultrasound (Fig. 2). The interface reduces the pin count and connections from 14 differential pairs to just two pairs. It is designed to connect to selected Altera, Lattice, or Xilinx FPGAs that support the interface. FPGA vendors refer to the JESD204B interface as a GTX transceiver.

2. The Analog Devices AD9250 features dual 14-bit, 250-Msample/s ADCs. Instead of 28 pairs of LVDS interfaces to the FPGA, this IC uses the JESD204B serial interface to cut interconnect lines to just two pairs.

Also, the AD9250 features 70.6 dBFS at 185-MHz amplitude input (Ain) and 250 Msamples/s, 88-dBc spurious-free dynamic range (SFDR) at 185-MHz Ain and 250 Msamples/s, IF sampling frequencies to 400 MHz, and 95-dB channel isolation/crosstalk. The power consumption of both channels at 250 Msamples/s is 711 mW with a 1.8-V supply. The package is a 7- by 7-mm 48-pin LF-CSP. A 170-Msample/s version is also available.

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