NXP want to replace that 8-bit micro with its new 32-bit, LPC800 based on Arm's Cortex-M0+ (Fig. 1). The 30 MHz chip comes in TSSOP16, TSSOP20, SO20 and DIP 8 packages and is priced under $0.39. The 2-stage pipeline provides a more deterministic execution environment needed for real time applications.
Figure 1. The LPC800 based on Arm's 32-bit Cortex-M0+ core.
The chips can have up to 16 Kbyte of flash memory and up to 4 Kbytes RAM. The system employs a 64 byte flash sector size. The smaller page size enables EEPROM-like capability. It is not quite to the byte-level of control but 64 bytes is not too bad.
There is also a 4 Kbyte ROM that hold device drivers and optimized power profiles. The ROM-based drivers can be used by themselves or in conjunction with operating systems like FreeRTOS. ROM is more efficient than flash. Using the drivers reduces flash requirements as well.
The chips can have up to 18 GPIO. A switch matrix allows most pins to be used with any of the digital peripherals. A state configurable timer (SCT) can be configured as one 32-bit timer or two 16-bit timers. It can handle PWM functions and the system supports inverted outputs.
Communication interfaces include up to three UARTs, two SPI ports and an I2C port. These interfaces can be used to wake up device.
There is an analog comparator that supports an external Vref input. It also works with internal voltage references.
LPCXpresso is NXP's Eclipse-based IDE. It is a free download but the tool is limited to 128 Kbytes of code. Of course, this does not matter with the LPC800 because it cannot have that much memory so the development tools are free.
32-bit platforms like the LPC800 can now challenge their 8-bit counterparts. They match or exceed the 8-bit platforms in price, chip size and power requirements. Common pinouts and availability of packages common to 8-bit parts make the LPC800 an ideal choice when moving to a more powerful but low power platform.
