Multicore Chip Downsizes

Nov. 3, 2012
Tilera's Tile-Gx9 packs in nine 64-bit cores tied together with its 8 Tbit/s iMesh on-chip fabric.

Tilera chips pack in lots of cores (see Single Chip Packs In 100 VLIW Cores) along with some hefty network interfaces as well. The Tile-Gx9 (Fig. 1) maintains the fabric architecture but reduces the number of cores to 9. This allows the chips to address low end embedded applications where the higher core count chips are simply overkill. The new chip has the advantage of reducing power requirements as well keeping the average power requirements under 10W.

Figure 1. Tilera's Tile-Gx9 chips packs in nine VLIW cores.

The nine 1.2 GHz, 64-bit cores are code compatible with Tilera's other chips. They are tied together with Tilera's iMesh 8 Tbit/s fabric. This allows easy migration of even multicore applications across the product line.

There will be 16- and 36-core versions (Fig. 2) that are pin-compatible. The 9 core version has a single DDR3 1600 memory controller compared to the dual port versions on the other chips. It also supports two 10 Gbit Ethernet/XAUI ports and up to a dozen 1 Gbit Ethernet ports. These are supported by the mPIPE packet processing interface.

Figure 2. Tilera's Tile-Gx9 is part of a three chip family that is pin-compatible.

The MiCA (Multistream iMesh Crypto Accelerator) handles crypto chores like IPsec and SSL at 10 Gbit/s speeds. The chip can also handle data compression and decompression at 5 Gbit/s.

Tilera's TILEncore PCIe Card (Fig. 3) includes a Tile-Gx9 chip. It plugs into a 8x PCI Express slot.

Figure 3. Tilera's TILEncore PCIe Card provides a development and evaluation that plugs into a standard PCI Express slot.

Tilera's 9 core chip can address a range of applications from network switching to proving image processing and video encode/decode services. The multicore architecture lends itself to scalable network appliances.


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