The circuit described here is a 12-V dc to 5-V dc (±5%) switched-mode power supply (SMPS). The supply uses a 12-V input from an array of four 3-V dc, 40-mA solar cells connected in series. (The cells are available for $3.75 each from www.Allelectronics.com.)
At the array’s maximum output of 12 V dc, its maximum output power is 12 × 40 mA = 480 mW. The supply’s efficiency is 83% ±1%. Therefore, the maximum output current at 5 V is:
(480 mW × 0.83)/5 V = 79.7 mA
This current might not seem like much, but complex designs may be powered by this modest current, especially if the parts in the design are low-power analog, or 4000-, 74CXX-, and 74HCXX-series ICs. Also, this is plenty of current for many of the new microcontrollers. On top of that, the cells take up only 120 cm by 120 cm.
The circuit is a step-down (buck) dc-dc converter that produces a positive output voltage that’s less than the input voltage (Fig. 1). U1 is a 35-kHz square-wave oscillator with a tH (high time) of 16.3 µs and a tL (low time) of 12.4 µs. The oscillator’s output drives Q1’s gate. During Q1’s (active low) on-time, the current through inductor L1, iL, increases sourcing current to filter capacitors C2 and C3 and the load. During Q1’s off-time, the energy stored in L1 flows through diode D1 and charges the filter capacitors.
D2 provides a 2.5-V dc reference voltage at U2a pin 3. R4 and R5 form a divide-by-2 voltage divider, resulting in a voltage near 2.5 V dc at U2a pin 2 when the output voltage is 5 V dc. If the voltage at U2 pin 2 is greater than 2.5 V dc (that is, the output voltage is greater than 5 V dc), the oscillator is disabled, which results in a very small amount of current drawn from the solar cells. If the SMPS output is less than 5 V dc, the oscillator turns on and charges the filter capacitors. In this way, the supply regulates the output voltage to approximately 5.0 V dc.
In a step-down SMPS, when the load resistance decreases, more current is required to maintain a constant output voltage. This means an increase in duty cycle and a corresponding increase in input current. However, because this design is powered by a 12-V dc, 40-mA solar-cell array, the current delivered to the SMPS must be equal to or less than 40 mA. Note that the no-load voltage at the solar-cell array is approximately 17 V dc.
The circuit provides power to the load equal to the input power multiplied by the efficiency. Figure 2 shows the solar cell’s output power at various times on a clear day. The measurements were taken in November with the solar-cell array parallel to the ground.
Using the measurements taken at noon,
VIN = 12.46 V dc, IIN = 34 mA, VOUT = 4.9
V dc, and RLOAD = 67 O.
PIN = VIN × i
PIN = 12.46 × 0.034 = 424 mW
POUT = (VOUT2)/R
POUT = (4.92)/67 = 358 mW
And the efficiency, E, is:
E = POUT/PIN
E = 358/424 = 84%
As mentioned earlier, the efficiency remains roughly 83% over the entire range of input power. The solar-cell output power values shown in Figure 2 were measured with a load voltage of 4.9 V dc.
The minimum load resistance at a given input power is:
R = (V2)/(E × PIN)
For example, at 11:00, the input power is 340 mW. The minimum R is (4.92)/(0.84 × 0.340) = 84 . Therefore, the maximum current available is I = V/R = 4.9/84 = 57 mA. Using this method, the available output current can be calculated from any input power.