Electronic Design

Cadence Turns To "Schedule Predictability Crisis" In RTL Design

Much of what's emerged from the Cadence/Verisity merger has been aimed toward addressing the lack of predictability in the verification process. Cadence has spent a good deal of time and energy crafting tools intended to manage the verification process. It's now turning that approach to the RTL front-end itself in a technology package it calls the Logic Design Team Solution.

In the RTL front end, there is a growing set of interdependencies that is compromising the predictability of the overall design schedule. These interdependencies fall across the domains of verification, power, design-for-test (DFT), and physical concerns. Changes in any one of these four areas ripples across the others and back again.

For example, designers are increasingly employing power techniques such as voltage islands and power gating that impacts the other areas. For sure, test vectors must be written to reflect the use of such techniques, so the power architecture must be considered when creating the test architecture. These power techniques also result in timing sensitivities, which in turn makes physical predictability that much more critical. All of these concerns need to be addressed in a holistic approach to RTL design.

Cadence's proposed answer to this dilemma is an integration of technologies from its existing Incisive functional verification suite and Encounter digital-IC design platform. To this foundation, the company plans to append a concurrent design architecture that mirrors the approach that it's taken to the functional verification problem. That is, you start with an executable design plan and a set of metrics to help determine when the project is completed. The management side of the equation enables the design team to look at the various interdependent domains concurrently. As a result, they should be able to reduce iterations not only within each of the domains, but across them as well.

Rather than relying on "design-for" terminology, Cadence is shifting to a "design-with" paradigm that stands on four "pillars," each of which addresses one of the four major areas of interdependence in RTL design. The overall methodology is a concurrent one that encompasses many technologies, synthesis being a key one but others including formal analysis, equivalence checking, test technologies, and static-timing technologies.

Tying the methodology together is overall plan-to-closure management and a logical sign-off procedure. Meanwhile, the pillars include:

  • Design with verification: early design verification including assertion-based formal analysis, simulation and acceleration, as well as verification management
  • Design with power: integrated low-power design and verification management across the front-end flow
  • Design with physical: reduces logical-physical iterations by providing accurate estimates of timing using physical engines from implementation within the logic-design environment
  • Design with test: integrates test with logic design to develop and debug a test infrastructure with minimal iterations
  • Design logical signoff: comprehensive implementation handoff checks and analysis to verify front-end closure with predictability
  • Design management: an automated plan and metrics-driven management system to track the progress of the evolving design against all functional, performance, and scheduling objectives.

Contact Cadence directly for pricing and delivery information with respect to implementation of the Logic Design Team Solution methodology.

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