Electronic Design

Flow Analyzes Process Variability

IMEC has developed a variability-aware modeling (VAM) flow that analyzes process variability of technologies below 45 nm. This flow enables designers to optimize their system design for timing, energy, and yield versus expected application load. The flow assesses the impact of process variations and degradation effects of these technologies on the system performance by giving valuable information to the designer.

IMEC, a Leuven, Belgium-based research center, developed VAM flow that can be linked into commercial design-for-manufacturing (DFM) tools and has been validated on industrial process technology data and IP cores. Also, this process analyzes information on process variability of sub-45-nm technology from the transistor up to the system level. The flow enables IP-block and system designers to make predictive assessments of architectural options and to identify design bottlenecks before manufacturing. In this way, functional problems and parametric uncertainty of their designs caused by process and material variability of deep sub-micron technologies can be overcome.

IMEC validated the VAM flow by propagating commercial TSMC 45-nm variability data to estimate performance and energy for an ARM926 processor. The VAM output was used to optimize the processor before manufacturing using a commercial tool flow.

Previously, most variability characterization work has been done internally by integrated device manufacturers (IDMs) on their own technology and IP blocks. But with the proliferation of fabless and so-called “fab-lite” semiconductor companies, IMEC hopes to bridge the gap between foundries and fabless companies on design-level impact of using most advanced semiconductor technologies. IMEC is inviting IDMs, fabless system companies, fabless digital IP providers, and foundries to collaborate within its Technology-Aware Design program. This program is trying to develop the necessary tools for designing reliable systems with variable and unreliable components. IMEC's program is compatible with confidentiality constraints for high value proprietary IP blocks.

Qualcomm and Samsung are the first top-tier industrial partners in IMEC's Technology-Aware Design program. IMEC has recently also signed a cooperation agreement with SI2 to pursue alignment with the industry standardization effort for statistical static timing analysis.


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