Wireless Systems Design

High-Powered Collaborators Produce Low-Powered SoC Demo

For next-generation wireless devices, longer battery life is a top-echelon design goal. But achieving that goal often requires expertise in multiple technology domains. Few if any single organizations possess such expertise. As a result, ARM, Artisan Components, National Semiconductor, Synopsys, and UMC have decided to funnel their individual technology strengths into a collaboration. The companies will deliver a comprehensive low-power, energy-efficient, system-on-a-chip (SoC) technology demonstrator for the ARM926EJ-S processor.

The Ultra technology demonstrator for the ARM926EJ-S processor is being implemented in UMC's 130e Fusion process. This 130-nm process platform was designed for the integration of high-speed and low-leakage transistors in a single CMOS process. The name "ULTRA technology demonstrator" stands for UMC Low-power Technology Reference using the ARM926EJ-S processor.

Each of the five companies in this collaboration has demonstrated technologies that contribute substantial power savings (SEE FIGURE). The combined power-savings capabilities of these technologies are expected to demonstrate up to 60% energy savings. For instance, the Ultra technology demonstrator will incorporate ARM's Intelligent Energy Manager (IEM) technology and National Semiconductor's PowerWise Technology advanced power controller (APC). The APC features an integrated hardware performance monitor (HPM) to reduce overall power and energy consumption. These combined technologies enable the Ultra system to implement adaptive voltage scaling (AVS) as well as frequency scaling. The system is expected to show the lowest voltage and frequency required to meet software deadlines. At the same time, it will maintain user quality.

Synopsys' Galaxy Design Platform also is part of the Ultra SoC technology demonstrator. This platform provides a low-power design-implementation flow, which includes multi-voltage and multi-frequency design optimization. To implement a complete SoC, the demonstrator will use Synopsys' DesignWare library for AMBA bus and peripheral IP. With this methodology, Synopsys Professional Services is providing the RTL-to-tapeout design services for the demonstrator chip.

Artisan's Metro product platform is the physical IP that enables the low-power technology-demonstrator design. It includes standard cells, I/Os, memories, phase-locked loops (PLLs), and other mixed-signal cells, which were designed for low dynamic and leakage power at any operating voltage. In addition, the products are characterized to operate at very low voltages. They can therefore allow the energy reduction enabled by ARM IEM technology.

Artisan's Metro platform, which was developed to address the power-management challenges in nanometer design, is based on a series of new architectures. Those architectures reduce power while enhancing density and yield. The result is power reductions of up to 80%, area reductions of up to 20%, and improved production yield.

The technology demonstrator will be enabled by UMC's advanced 130-nm Fusion process, thereby creating a low-power SoC while minimizing performance tradeoffs. The SoC resulting from the collaboration is not intended for sale. Instead, it will be used to demonstrate the unique and combined capabilities of the five companies when applied to the problem of IC power conservation.

TAGS: Intel
Hide comments


  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.