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Electronic Design

Triple-Well Process Cuts Flash-Memory Storage-Cell Size, Boost Performance

A triple-well channel-erase NOR technology promises higher density and faster flash memories. Initially, the process will be used by Hyundai Electronics America, San Jose, Calif., to produce 16-Mbit flash memories implemented with 0.35-µm design rules. Plans are already in motion, however, to quickly convert to 0.25-µm design rules for higher-density devices. When fabricated on the smaller design rules, the memory cell size is just 0.69 µm2.

Through the triple-well structure, designers can reduce the channel length of memory-cell transistors by about 20%. Although the channel is shorter, its width is slightly expanded (by about 10%). The wider channel increases read performance for low- and super-low-voltage operation. Overall, the storage cells are 10% to 20% smaller than cells of competing flash memories created at similar design rules.

In conventional, second-generation negative-gate source-erase NOR technology, the memory cell is typically fabricated on the p-type silicon substrate (see the figure, left). The triple-well process, however, forms the memory cell inside a p well. This p well is, in turn, built within an n-well (see the figure, right).

Because the triple-well structure forms symmetrical shallow source and drain junctions, the manufacturing process offers a simpler fabrication sequence than most other flash processes. It also eliminates band-to-band leakage current at the source junction during the erase operation. This results in a low-energy erase operation and no hot-hole-related degradation, which means better endurance and data retention.

To erase the data, the channel-erase operation applies a positive voltage on the p well and a negative voltage on the control gate. By doing so, blocks of the flash memory can be simultaneously erased out without consuming a lot of current. The low current consumption eliminates the band-to-band tunneling problem, which in earlier flash devices could lead to reliability problems.

In band-to-band tunneling, 5 to 12 V is used to bias an n+-p junction. Such a high voltage causes the silicon's band structure to become severely banded near the junction. Electrons can then tunnel through the junction, generating a great density of high-energy electron-hole pairs. These pairs can be trapped in the tunnel oxide and lead to reliability problems.

With the absence of band-to-band tunneling and the high current consumption associated with it, data retention and cell endurance are improved. Additionally, there's no longer any stress-induced leakage current because the tunneling problem has been resolved. In addition, the oxide thickness is up to 15% less than that in conventional flash memory structures.

Thinner oxides also prevent a large buildup of hot holes, which minimizes the charge leakage from the floating gate to the substrate. Furthermore, it eliminates leakage current that can migrate from the substrate to the floating gate during a read or storage operation. As a result, the memories have improved data-retention capabilities.

Another benefit of the triple-well structure is that the channel-erase technology keeps the post-erase array threshold voltage (VT) distribution about 20% tighter than that of most second-generation flash technologies. Effects of this include a lower VT level after erasure, a higher read current which lets the memory access faster, and reduced occurrences of over-erased cells for greater endurance.

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