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Why is PDN measured using a VNA and not an oscilloscope?

Sept. 10, 2013
Steve Sandler answers a reader question about why PDN voltage is measured using a VNA instead of a oscilloscope.

QUESTION: If PDN (Power Distribution Network) analysis is an assessment of the input power supply voltage to a CPU then why is it measured using a VNA and not an oscilloscope?

ANSWER: First, your understanding of PDN is largely correct.  The PDN includes the voltage regulator, printed circuit board traces or planes, vias and decoupling capacitors including the capacitor series resistance (ESR) and inductance (ESL).  The voltage arrives at the load (CPU) and must be within allowable regulation limits.  Internal to the CPU, the bond wires and die capacitance also form part of the PDN.

While CPUs can be difficult to assess from the PDN perspective FPGAs can be as or even more difficult due to the higher edge speeds.  The spectral content of many high speed FPGAs can be as high as 10GHz, requiring the PDN assessment to include the content from DC to 10GHz. It is clear that only computing the DC input voltage regulation range is insufficient.

Since we are interested in monitoring the voltage at the output of the regulator but including all of the pathways to the pins of the load (CPU or FPGA) it would seem that the best tool would be the oscilloscope, which allows us to directly view the voltage in the time domain. However, a fundamental limitation is that we do not know the load current pattern, since that is determined in large part by the software contained within the CPU or FPGA. It may not be obvious, but the output voltage is a function of the load profile and its reflection through the AC impedance to the regulation to a large degree. Therefore, capturing the voltage excursions of interest requires coordination with the FPGA operation. A resistive PDN and associated load pattern is shown in Figure 1. The same load pattern applied to a PDN with a single anti resonance, caused by the load impedance, is shown in Figure 2.

Figure 1. Load current patter (green trace) and voltage response (yellow trace) for a resistive PDN.


While there is nothing particularly notable in Figure 1, the response shown in Figure 2 indicates two distinctively different responses. The first, natural response results in a damped ringing due to an underdamped antiresonance. The second or forced response is related to the current burst in the center of the load current pattern.

The natural response is the response of the regulator to a load step where by the output voltage is allowed to settle before then next load transient is applied. The forced response is when the load step is applied sometime before the output response has had time to settle. In that case, subsequent load transients can reinforce themselves creating output voltage excursions that are greater than the natural response produces. The behavior is a function of the bandwidth of the regulator.

Therefore, if the regulator’s bandwidth is very close to, or a multiple of, the antiresonant (peak in the AC impedance, See Figure 6) frequency the result can be a growing output voltage waveform. The amplitude of this response will eventually settle to a fixed level after a number of cycles, dependent on the antiresonant Q. Many antiresonances can occur in the PDN range of DC - 10GHz, with each antiresonance exhibiting these interactions with the regulator and load step profile.

Figure 2. Load current patter (green trace) and voltage response (yellow trace) for a PDN with a single resonance.


While it would seem to be appropriate to measure the transient response of the PDN using an oscilloscope it is not as easy as it sounds. Measuring in the time domain requires us to provide the dynamic current stimulus and therein lies the issue. The Picotest J2112A Current Injector is much faster than an electronic load with a typical response time of 10nS as shown in Figure 3. It can also be controlled using an AWG making it ideal for generating irregular load profiles.

Figure 3. Measuring response using an oscilloscope

This solution is acceptable for many lower power devices of 1.2V and above, however, FPGAs can be much faster and with much larger current changes than current injectors can generate.

Another possible solution is to write software using the FPGA to create the repetitive load profile. The only problem is that we do not know what the worst current profile looks like given the target impedance, and therefore, do not know how to create it. [Ref. 1]


The RF Vector Network Analyser (‘VNA’) can easily measure impedance over a very wide frequency range. The OMICRON Lab Bode 100 offers a range of DC-40MHz. The Agilent E5061B can measure up to 3GHz and there are several VNAs that can measure to 10GHz or more.

The two-port RF VNA measurement can very accurately measure milliohm resistances consistent with an FPGA. Several application notes are referenced at the end of this post. [Ref 2]

Figure 4. A low cost RF VNA and common mode transformer can measure 1 milliOhm
Figure 5. Measurement showing the 1.3 milliOhm resistance and 500pH inductance

The theory behind target impedance is very simple, essentially using Ohms law to relate the voltage change as the product of the current change and the impedance of the path from the regulator to the FPGA. Though FPGAs do not always state it, the target impedance required for proper operation is the AC impedance of the path including all series and shunt loading, is usually a not to exceed impedance value with the goal of having as flat a response as possible.

At DC this works, though with AC signals the impact of the varying impedance isn’t quite that simple.
Of course we can solve this for Z
Therefore, we have converted the FPGA’s input voltage requirement (output of the regulator) to the impedance domain where we can more easily assess it. As a rule of thumb, many engineers assume that the FPGA current change can be up to 50% of the maximum operating current. The example impedance simulation in Figure 6 shows a PDN with a target impedance of 125 milliOhms and three antiresonances.
Figure 6. A simulated impedance response showing three antiresonances each with a peak impedance within 125 a miliiOhm limit


In our sample case, applying a 2A dynamic current change (from the FPGA as seen by the regulator) should theoretically result in a regulator voltage change of 250mV. Yet the simulated output of the regulator shown in Figure 7 is clearly significantly greater. At the rising edge of each of the initial bursts, we can see the three different ringing frequencies. Since the three antiresonant frequencies are broadly spaced, it is difficult to see the highest frequency while the other two frequencies are much more obvious. This is another advantage of the RF VNA measurement vs. the oscilloscope, in that the log sweep makes it much easier to identify these broadly spaced responses.

Using the ADS simulation optimizer we can determine the worst case current profile that results in the largest voltage excursion, shown as 559mV in this simulation. A closer view of this excursion is shown in Figure 8.

Figure 7. Dynamic load current change and voltage response
Figure 8. Closeup view of Figure 7 Therefore, a more realistic assessment of the output voltage based on the output impedance measurement is:
Where i represents each antiresonance in the impedance measurement. A detailed examination of this can be found in a recent article Target impedance based solutions for PDN may not provide a realistic assessment referenced at the end of this post.
Figure 9. A real world example showing two low frequency resonances.  The blue trace is the current signal and the yellow traces is the voltage response.  The green trace is just the function generator trigger output.

So why is the PDN assessment so important for power systems designers to understand?

The most important concept to understand about PDN is that the FGPA’s data pattern induced load current profile causes ‘forced’ load step responses on the regulator that are superimposed on one another causing the voltage excursions to be larger than one would otherwise think. This is why the regulator’s regulation range can exceed the FGPAs input limits causing potential catastrophic consequences to the performance.


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