A RISC Approach to SONET Testing

What worked yesterday may not work today and could easily be obsolete by tomorrow. Such is the case with synchronous optical network (SONET)-based test equipment, where the survival of the networks depends on the right testing tools.

Much of the SONET test equipment used today is based on the same chip sets used in SONET transmission equipment. True, these off-the-shelf chips can reduce the initial cost of building SONET testing tools. But they also can limit features and create a design that fails the first requirement of SONET testing–flexibility.

To accommodate new SONET payload mappings, such as fiber distributed digital interface (FDDI) or asynchronous transfer mode (ATM), and to respond to customer-driven requests, test equipment must be able to adapt to changing standards. With a commercial chip set, SONET functionality may be cast in silicon, which can prevent or delay the accommodation of new features into the product.

Fortunately, this problem can be solved by using a high-speed reduced instruction set computer (RISC) microprocessor, a field-programmable gate array (FPGA), and dual-ported random access memory (RAM) instead of a commercial chip set. Since the processor’s program and the FPGA contents can be both modified and enhanced through simple software upgrades, this design provides a low-cost, space-efficient and highly flexible SONET testing solution.

Using RISC for SONET Analysis


Coupling a microprocessor with an FPGA takes advantage of the best of two worlds. In the same way that a computer can be reprogrammed, the registers and combinational logic in an FPGA can be rewired to perform a variety of operations. An FPGA can be programmed to process a serial stream of data efficiently, where each piece of data needs to be manipulated only once and sent on its way. For this reason, an FPGA is an excellent place to perform a repetitive, single-cycle operation like the SONET scrambling and descrambling operation or the calculation of the section and line bit interleaved parity (BIP) values.

But a processor is much better than an FPGA at performing operations that require remembering information or multiple accesses to the same data, such as accumulating SONET statistics or error counters. A processor is also better suited for operations that require complex logical decisions, such as those based on range comparisons.

A SONET receiver block diagram is shown in Figure 1. The FPGA essentially functions as a data formatter, descrambling and writing the SONET data stream into dual-ported RAM in fixed locations.

The processor reads this data out of the dual-ported RAM, detects any SONET alarm conditions, and collects statistics and results. The embedded payload is extracted from the SONET data by the processor and sent on for further analysis. The collected results and alarms are available for formatting and displaying at the test set user interface.

A SONET transmitter uses the same basic design, but all the data flows in the opposite direction (Figure 2). The processor writes an input payload to dual-ported RAM in the proper SONET mapping format; that is, a DS1 structured as a floating, byte-synchronous VT1.5 payload.

The processor also places the values of all the SONET overhead bytes into the dual-ported RAM. The transmit FPGA is responsible for reading out the payload and overhead information, combining them, calculating the proper section and line BIP values, and scrambling the signal for transmission.

A double-buffered approach allows the FPGA and the RISC processor simultaneous access to the SONET information in the dual-ported RAM. As shown in Figures 1 and 2, while the processor decodes the payload and overhead information in Bank #1, the FPGA is writing new information into Bank #2. Since the basic SONET frame rate is 8 kHz, the RISC processor must decode the entire payload in less than 125 us.

Since the drop and insert of subrate payloads is handled entirely by the RISC processor, support of new payload types is accomplished through software enhancements. In contrast, hardware modifications and additional customer ICs may be required to support additional SONET payloads when a commercial chip set is used.

Using the SONET Structure


Because the RISC processor has access to each and every byte of the SONET overhead and payload, it can perform operations that would not be possible with an off-the-shelf SONET controller chip. For example, the SONET overhead carries information that describes the type of payload being carried. But this information may not always be valid or complete.

Due to the processor’s low-level access to the SONET data stream, it can actually examine selected portions of the received SONET data to determine the type of payload. This approach to payload detection can be extended to new or additional payload formats through software upgrades, and would be impossible to implement without the aid of a high-speed RISC processor.

Since the transmit-side processor is responsible for producing each overhead byte in each SONET frame, some very precise and sophisticated error and alarm conditions can be generated. For example, subtle modifications to the SONET framing bytes can be made to exercise the loss of frame criteria on the SONET transmission equipment under test. Similarly, complex sequences of path-pointer values can be generated to explore the effects of pointer movement and its associated jitter effects in SONET network design.

Monitoring an in-service circuit and simultaneously inserting errors and alarms is another critical application for SONET testing. The FPGA/RISC combination is uniquely suited to this through-mode analysis. As shown in Figure 3, the receiver FPGA loops the received SONET information back to the transmit FPGA and makes it available for decode and analysis by the receive RISC processor.

The transmit FPGA can combine the receive SONET payload with modified overhead information from the dual-ported RAM. In this way, unique errors and alarms can easily be added to the live SONET signal while simultaneously allowing full SONET analysis and payload drop.

Conclusion


Off-the-shelf SONET analysis components can limit the flexibility and growth of a SONET test set. The FPGA/RISC combination is a versatile solution that has proven itself in the fast-changing SONET marketplace.

For example, Telecommunications Techniques Corp. added SONET OC-3c testing to the T-BERD 310 SONET/DS3/DS1 Communications Analyzer by revising the FPGA program and writing additional mapping software for the RISC processor. By working within this same design structure, other testing scenarios and SONET mappings (such as ATM cell generation and decode) can be added.

The right tools to test SONET are a matter of network survival. But confidence in SONET tools should be measured in the design of the tools themselves and their capability to meet emerging SONET testing needs.

About the Author

 

Thomas A. Bahls is a Senior Software Engineer at Telecommunications Techniques Corp. Before joining TTC five years ago, he was employed by Hughes Network Systems. Mr. Bahls received a B.S.E. degree from the University of Michigan. Telecommunications Techniques Corp., 20400 Observation Dr., Germantown, MD 20876-4023, (301) 353-1550.


Copyright 1995 Nelson Publishing Inc.

January 1995

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