Success With Boundary Scan

One leading electronics manufacturer has successfully implemented boundary scan technology and other test strategies to achieve 100% fault coverage and a 245% return on investment in manufacturing test. By re-engineering one of its manufacturing processes, the company was able to achieve significant competitive gains.

Matsushita Electric Industries is the second largest electronics manufacturer in the world, and the largest in Japan. It is one of the world’s premier manufacturers of electronic equipment for home, industrial and commercial use. Its products include TV, video tape recorders (VTRs), TV cameras, camcorders and audio equipment with brand names such as Panasonic, Quasar and Technics.

As with any leading-edge company, Matsushita long ago recognized the key trends that impact the manufacture and test of new products. These trends include significantly more digital components in new consumer and professional electronics products; reduced nodal access on PCBs; and an increasingly competitive marketplace, requiring more cost-effective manufacturing and test methods.

Matsushita’s Audio and Video Research Laboratory (AVRL), in Osaka, Japan, was charged with addressing these trends through new device, manufacturing and test technologies. The laboratory’s strategy was to obtain 100% fault coverage as early as possible in the manufacturing process. One hundred percent fault coverage is defined as testing for opens and shorts on all solder joints, checking the presence and basic function of all components, and verifying as many IC pins as possible for damage due to electrostatic discharge. Bypass capacitors and parallel VCC and GND pins are excluded from the 100% fault coverage requirement.

To appreciate the changes Matsushita made, it’s important to examine the company’s prior test strategy. After the PCBs were produced, they were subjected to in-circuit test (ICT). After ICT, electrical adjustments took place, followed by a final hot mock-up test. The average test time per board (including repair) was 5 minutes for the ICT and 30 minutes (in some cases, up to two hours) for the hot mock-up test, including handling time.

Matsushita’s assembly yield was about 85%, meaning that 15% of the boards going from assembly into test were faulty. Fault coverage at ICT was around 70%, meaning that 70% of all faults were detected. As a result, the yield of good boards after ICT and repair was 95%. The remaining faulty boards were not detected until the hot mock-up test, and even then some defects were not found until final assembly test.

The old test paradigm required as many test pads as there were nodes, but component density of new boards limits the number of test pads available. Worse, the larger the ASICs became, the more complicated the test-pattern library. This made test development more difficult and time-consuming.

Clearly, the former board test strategy was no longer adequate. A new way of thinking about test was imperative.

A Solution Emerges

After researching various partnering opportunities, Matsushita selected Hewlett-Packard Co. to jointly rethink their manufacturing and test process, using HP’s complement of test solutions, including HP InterconnectPlus boundary scan technology.

In 1992, Matsushita selected two VTR boards as models to conduct a thorough analysis of their current manufacturing and test processes. The boards are part of a new Panasonic professional VTR which will be used as the key broadcast recorder for the 1996 Olympics in Atlanta. When the boundary scan project began, the boards were in the early design phase.

One of the boards, 11.5 cm x 18 cm, featured these characteristics:

o 1,377 nodes

o 5,299 solder joints (4,593 testable; the untestable joints are on the parallel VCC and GND pins)

o 450 discrete analog components

o 78 RAM and glue logic ICs

o 9 ASICs with boundary scan

o 3 ASICs without boundary scan

o 6 PLDs

No single test tactic was adequate to achieve 100% fault coverage. With HP’s technical direction, a set of seven test tools was selected and implemented to respond to the mix and high density of components on the board: The combined use of HP TestJet, HP InterconnectPlus boundary scan technology, and partial library tests made the improved fault coverage possible in spite of decreased access to test points.

The mixed set of seven tests applied to achieve 100% fault coverage is described here. The first three steps are run unpowered.

1. Shorts–The first step is a conventional shorts test, where probe access is available. This test by itself could not find all possible shorts, given the limited nodal access.

2. Analog In-Circuit–The next test step is analog in-circuit measurement of all discrete analog components. Since the goal is to test 100% of all components, nodal access is required for all of them.

3. HP TestJet–Three ASICs on the board are not boundary scan devices. To test the solder-joint integrity on these components, HP TestJet is used.

At this point the board is powered up.

4. HP InterconnectPlus Boundary Scan–This is a set of different tests designed to find shorts as fast as possible, then to test for opens.

5. HP Silicon Nails–This test further reduces the need for nodal access on 25 simple components, such as buffers, latches and static RAM–components without boundary scan circuitry. In this case, a mixture of physical test channels and boundary scan resources is used. In some cases, these conventional components could be tested without nodal access, using boundary scan resources exclusively.

6. Digital In-Circuit–Some digital components are tested with conventional digital in-circuit test methods.

7. Partial Library–The components tested with HP TestJet still require test for orientation and basic function. The solution is called partial library test. With a full library test, it is relatively easy to get 25% to 50% fault coverage. Good test coverage for the next 30% to 40% takes significantly longer, and finding a test for that last fault may take weeks or months.

In this case, HP TestJet has already tested the solder joints of the pins, so the library test does not need to check all pins. Instead, an easy, quickly developed test is adapted from the early steps of a full library test, incorporating significant fault coverage and the capability to test basic function and orientation of the device.

With these seven major test tools, Matsushita achieved the goal of 100% fault coverage.


The new test strategy achieved several noteworthy accomplishments:

o Eliminated hot mock-up test. With the new process incorporating both in-circuit, boundary scan and partial libraries test, the fault coverage at ICT became 100%. This is a significant achievement in manufacturing test.

Eliminating the hot mock-up test shortened anywhere from 30 minutes to 2 hours of the test time per unit in the manufacturing process. Elimination of this test step has a direct impact on the overall manufacturing cost of the board.

o Distinguished between design faults and manufacturing defects early in the product life cycle. When designing a board, several iterations occur between design and production. Test results using the old test strategies could not tell the designer whether a fault was due to design or a manufacturing error. Several iterations of a prototype could be required, each taking three to six months.

Boundary scan circuits make it possible to test for manufacturing faults regardless of whether the board functions correctly. With boundary scan, it is possible to find 100% of the manufacturing faults, so the only faults left–if a board did not function correctly–are guaranteed to be design errors.

Designers were quickly able to observe design faults and correct them before manufacturing began. This reduced the number of iterations, speeding time to market.

o Reduced probe count for in-circuit test by 15%. Normally, if test points are reduced, so is fault coverage. This is no longer the case with boundary scan. The boundary scan components negated the need for test points while improving fault coverage. This project was able to eliminate 200 test points out of 1,377 nodes while improving fault coverage to 100%.

o Reduced test development time by one-third, and reduced board design time by three to four weeks. Writing a test for an ASIC may take two to three months. With boundary scan technology, this is reduced to a couple of hours because the test process is automated. Since boundary scan incorporates better fault diagnostics and requires less fixturing, both design time and fixturing time are reduced.

Return on Investment

Any change in process implies expense, and Matsushita monitored its costs carefully. Because boundary scan circuitry must be designed into the components, there was a concern that the ASIC’s unit price would go up with the related increase in device area.

In fact, this was found to have only minimal impact. IC costs were only 1% to 5% higher than non-boundary scan ICs, and were more than offset by eliminating the hot mock-up test and shortening time for repair.

Besides increased ASIC costs, there were necessary investments in electronic design automation tools to complement the new procedure. After calculating cost increases and decreases throughout the entire production cycle of the VTR boards, the return on investment (amount saved due to introduction of the procedure divided by the net investment amount) was 245%. Because of these results, Matsushita is introducing this process into other divisions.


The Force Behind Boundary Scan at Matsushita

With a hundred patents to his credit, Teiichi Owaki, Assistant Councilor of the Audio and Video Research Laboratory (AVRL) at Matsushita, is an acknowledged visionary in audio and video technology. For more than 30 years, he has pioneered significant technological advancements in the home-entertainment industry.

Notable among his achievements was the development of the VHS format for video recorders. He recognized early on that the Beta format with its 2-hour maximum recording time was unacceptable to the American consumer. After all, that wasn’t even long enough to record a football game.

In 1976, as leader of a 100-engineer team, Mr. Owaki developed the VHS format for in-home video recorders, and six-hour videos became a reality. The team was responsible for developing low-cost, high-performance, easy-to-use portable recorders that changed the consumer video marketplace.

In 1987, Mr. Owaki was appointed Planning General Manager of the AVRL and charged with the responsibility of defining the operating philosophy for digital video and electronic image technology. Later he played an instrumental role in developing a partnership with HP to incorporate boundary scan technology in Matsushita’s new products.

As a direct result of this effort, Mr. Owaki was given the Silver Award, Matsushita’s annual prize for innovative technology achievement. The prize honored the successful integration of boundary scan technology with complementary test solutions to achieve 100% fault coverage on new VTRs.

Copyright 1995 Nelson Publishing Inc.

February 1995

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