The gap between the infinite timing freedom of digital IC design and the limited functionality of today’s ATE is driving an evolution in test technology. Proof of this change is the recent innovation of waveform-oriented tester architectures emerging to compete with the traditional approaches that feature hardwired formats.
The traditional implementation of Change Timing on the Fly is failing to meet the needs of advanced digital device manufacturers. To compensate for this inadequacy, three main waveform architectures are now gaining acceptance as better alternatives.
Change Timing on the Fly
As digital IC test systems evolved during the 1960s, their timing complexity increased with each new generation. Simple data formats, such as non-return-to-zero, became augmented by more complex application-focused formats, such as Surround-by-Complement. In the 1970s, Change Timing on the Fly was added to cope with complex device timing and production throughput requirements.
Change Timing on the Fly does not describe a standardized set of capabilities. Almost every type of digital ATE features a different timing architecture. However, there are certain commonalities among most Change Timing on the Fly implementations.
For example, timing generators can be reprogrammed from one test vector to the next. As a result, the timing position of an edge changes in relation to the cycle boundary.
This reprogramming of edges needs a certain amount of time, and even though today’s advanced technology can keep this down to a few nanoseconds, it still causes dead zones at high data rates (Figure 1). Also, it is difficult to achieve highly accurate edge timing when reprogramming edges on the fly. As a result, some ATE systems specify accurateless accurate time sets. and
Finite edge programming time and potentially limited accuracy make it hard to implement traditional Change Timing on the Fly techniques for ATE running at more than a 100 MHz.
With most ATE systems, it also is possible to change data formats on the fly from one test vector to the next. However, users are still limited to formats available in their test system’s hardware. Nonstandard waveforms would need a hardware redesign.
An increasing number of high-complexity devices feature multiple independently pipelined buses. Bus activities, such as writing to a processor’s cache while reading from a peripheral circuit, are performed clock-synchronously but fully independently of each other so that each bus has its own sequence of device timing.
Traditional ATE use a system-wide time-set select, limiting testability for this type of device. A per-pin time-set select would be more suitable.
Design departments undertake extensive simulation of new circuits. The simulator output data is the source for test vectors and timing. The translation of one into the other is far from smooth, requiring work-arounds to bridge the gap between the timing freedom of IC design and the limits of ATE hardware.
These physical limitations of Change Timing on the Fly implementations are forcing test engineers to develop work-arounds and even to accept reduced test coverage. Compounding the situation is the intense economic pressure on IC manufacturers. Market prices of new ICs get slashed very quickly.
In today’s IC business, manufacturers must maximize device quality while paring costs to the bone. Testing compromises can no longer be accepted and the ATE vendors must face customer demands for greater timing flexibility.
At first, the ATE industry responded by simply renaming traditional hardwire format concepts, coining the buzzword “waveform.” However, a few ATE vendors quickly saw that a true waveform-based timing concept could help fulfill both the demands for high timing flexibility and reduced cost.
Change Waveform on the Fly
The new implementation of Change Timing on the Fly can be described as Change Waveform on the Fly. It is based on the idea of storing a number of user-definable waveforms in each pin’s hardware (Figure 2). One of these waveforms can then be selected for each of the tester cycles. The sequence of waveforms is controlled by a waveform selector that points to just one waveform per tester cycle.
For an actual test program, the waveforms and their sequence are translated from design simulation data. For clarity, this discussion will focus only on the drive signals, but the concept will be valid for comparator signals too, as the Change Waveform on the Fly approach generates them in the same way.
Three Concepts
o Design simulation results in lists of events for each device pin. One approach would emulate those events in digital system hardware. Individual waveforms are defined by a list of events consisting of timing-edge positions and related actions (Figure 3).
This architecture promises maximum timing flexibility. However, functionality is still somewhat constrained by the available technology, resulting in the number of programmable events and implemented timings being compromised.
For the actual implementation, timing edges could be programmable on the fly. Combined with the capability of those edges to be reused during one tester cycle, this concept delivers high timing flexibility without passing the barriers of technology. On the negative side, it is still limited by dead zones caused by timing-edge programming times. Still, it does not match the infinite timing freedom of design simulation.
o A second new Change Waveform on the Fly concept is simpler: tie actions to each of the timing edges available. The edge positions are fixed during a particular functional test, and individual waveforms are generated by programming sequences of 1s and 0s into a waveform memory (Figure 4).
A 1 gets the action executed at its related timing edge. A 0 causes no activity. Different device data would be programmed into different waveforms. The content of each test vector points to the waveform to be executed in the current tester cycle.
The ease of implementation is offset by the requirement for a large amount of timing edges. For example, to generate a traditional surround-by-complement, six edges are required. Additional timing conditions during the same test run need additional hardware edges.
o A third concept achieves higher timing flexibility by programming each of the waveforms as a sequence of actions. A series of actions is executed for each test vector. Timing edges are fixed in their position but can be used for different actions (Figure 5).
The waveforms contain data and device timing information. The content of a test vector points to the waveform being used in the current tester cycle. Changing an edge position in the traditional sense is performed by doing the same action on another timing edge.
This concept combines high timing flexibility with low cost. The limitations of traditional Change Timing on the Fly architectures, such as minimum edge repeat rates or inaccurate time sets, do not exist. Each pin generates its own sequence of timing to serve devices with independent buses.
Summary
There is a gap between the infinite timing freedom of digital IC design and the technical implementation of digital test equipment. Traditional format-oriented tester architectures are bridging this gap with various Change Timing on the Fly implementations. Besides inherent limitations, these approaches are expensive.
February 1995