Vectorless Test Boosts Fault Coverage and Cuts Cycle Time

New vectorless test techniques are being embraced by test-equipment users with an enthusiasm not seen since the introduction of in-circuit test (ICT) itself. The use of vectorless test is probably as significant a manufacturing test paradigm shift as was the use of ICT to replace functional test as the mainstream test methodology.

Vectorless test methods are well-suited for finding pin-related process faults on SMT boards. They use analog stimulus/measurement approaches in contrast to traditional in-circuit digital backdrive methods, which require the application and measurement of patterns (vectors) to assess pin integrity.

These power-off technologies can be considered a breakthrough in reducing test development time while improving fault coverage. A test for any IC can be developed in minutes, regardless of size or complexity.

This compares quite favorably to the days or weeks that are typically required for the creation of test vectors. No device information is needed to create a test for the device. Diagnostic resolution is to the actual failing pin.

The three primary vectorless techniques are analog junction test, radio frequency (RF) magnetic inductive test, and capacitive coupling test. Each has advantages and limitations.

Analog Junction

The analog junction technique performs simple DC current measurements on unique pairs of device pins to find pin-related faults. This technique works by measuring the change in current at a node caused by the injection of a secondary voltage source to a pin pair (Figure 1).

Unlike previous passive measurement approaches, this technique measures characteristics of devices that have been explicitly designed into the device: the electrostatic discharge (ESD) protection diodes that are intrinsic to all digital ICs and most analog devices. Device variations from lot-to-lot process changes and the use of different device vendors do not generally affect the measurement’s accuracy because the change in current, rather than an absolute value, is measured.

This is how the technique works:

1) A negative voltage (with respect to ground) of up to -0.9 V is applied to Pin A, causing current (i_a) to flow through the forward-biased diode on Pin A.

2) While this voltage is maintained on Pin A, a larger negative voltage (-1.2 V) is applied to Pin B, causing current (ib) to flow through the forward-biased diode on Pin B. Due to the current sharing in the common substrate resistance from Pin A and Pin B to ground, ia flowing through the diode on Pin A decreases.

3) Again, ia is measured. If there is no change in ia when the voltage is applied to Pin B, then a connection problem exists.

4) The test results from the many possible pin pairs on the device are combined to give a precise fault diagnosis.

The signal pins, power and ground pins, and the substrate participate in the analog junction test. Consequently, other common manufacturing faults–in addition to pin opens–can be detected, including missing devices, misoriented devices, bond wire opens, and opens on single ground pins.

The analog junction technique offers several advantages over other vectorless techniques:

It requires no fixture hardware such as overclamps, sensors and inducers. Any existing ICT fixture can be used.

The measurements are very fast, typically a few milliseconds per pin.

This technique detects other fault classes besides opens, including misoriented devices, open bond wires and ESD damage.

It works with virtually any IC package type, including ball grid arrays (BGAs) and devices with heatsinks and ground planes.

This technique does have some limitations:

It requires the presence of protection or parasitic diodes. Device pins without protection diodes, such as some pins on linear or passive devices, cannot be tested.

If a device lacks unique pin pairs, it cannot be tested.

Large capacitors on a net will prevent this technique from making a stable measurement within the allowed measurement window, resulting in a net that is considered untestable.

RF Magnetic Induction

A second vectorless technique is based on electromagnetic measurements. It uses the transformer principle to measure the presence or absence of a current path on a given device. This technique checks for continuity between the device lead and the board with RF stimulus and measurement. Like the analog junction technique, the RF method takes advantage of the protection diodes in the chip (Figure 2).

This is how the RF magnetic induction technique works:

1) A fixture-mounted de-multiplexer board connects the magnetic inducer mounted over the selected device to be tested.

2) A transceiver (mounted in the test system) sends an RF signal (200 kHz to 500 kHz, 0.3 V peak-to-peak) to the selected inducer.

3) The low-frequency signal (200 kHz to 500 kHz) emitted by the inducer creates a magnetic field, producing an AC voltage of a few hundred microvolts in the DUT in the same way as a transformer induces an AC voltage in a secondary loop.

4) The transceiver measures the induced AC voltage on each device pin. If there is a complete circuit within the device, then the AC signal can be measured via the tester’s bed of nails.

If an open exists anywhere in the circuit path between the device and the tester pin, the AC signal will not be present. In this way, any break in the path is detected. In practice, the AC signal is too small to forward-bias the protection diodes, so an external DC current bias source of 1 mA to 20 mA is used, with the AC voltage superimposed on the DC voltage.

This method uses the chip’s power and ground pins to make its measurement, which tests the integrity of the entire circuit path within the chip’s die. As a result, it not only finds solder opens on device signal pins, but other common faults as well including broken bond wires and blown buffers damaged by ESD.

Because this method uses the device’s power and ground pins as an integral part of the measurement circuit, a ground pin in the wrong place can be detected easily, enabling it to find misoriented components. It also detects power pin opens on components with a single ground or power pin.

The RF magnetic induction technique has several benefits:

It is usable on leadless package types such as BGA, pin grid array (PGA) and chip-on-board (COB) because a rotating magnetic field cuts a conduction path as opposed to measuring the capacitance of a mechanical element of the device such as a leadframe.

The inducer does not have to fit precisely over the device package. Typically, one of four inducer sizes can be used to test a device as opposed to requiring a sensor plate that closely matches the package outline size of the device. As a result, the user does not have to stock a large variety of sensor plates for fixture build or refurbishment.

It can detect fault classes such as rotated IC packages and wrong device type as well as open power and ground pins, because the technique requires that a DC bias current be present on the pin to be tested.

The RF magnetic induction technique does have some limitations:

It requires the presence of an ESD protection diode.

Like the capacitive technique, the RF technique requires that an external inducer be mounted over the device being tested.

There may be some sensitivity to board layout and node topology that will prevent inspection of certain pins.

This technique does not work on connectors and other passive devices.

Capacitive Coupling

The capacitive coupling technique measures the sub-picofarad (<10-12 F) capacitor formed by the leadframe of a device package (PLCC, QFP, DIP), the device package material, and an external plate placed on top of the device being tested. Unlike the analog junction and RF magnetic induction techniques which rely on internal device circuitry, capacitive coupling relies on the presence of the metallic leadframe of the device to test the pins (Figure 3).

This is how the capacitive coupling technique works:

1) An analog test board mounted in the test system sends an AC signal to the pin-under-test.

2) The capacitive probe picks up and buffers the AC signal from the device-under-test pin.

3) The multiplexer board (mounted in the fixture) selects and amplifies the signal.

4) The analog test board measures the AC voltage for each device pin. If the device pin is connected correctly to the board, the presence of a signal can be measured on the sensor. If the pin is open, no signal is present.

The capacitive coupling technique provides significant fault detection capabilities for solder opens on IC leads, the most common SMT process fault. Other benefits include:

Can be used on any IC device having an internal leadframe. The type of device–linear, mixed-signal or digital–is not important, and ESD protection diodes aren’t required on the pin.

Can detect opens on many SMT connectors and sockets.

Can be used to test a variety of SMT connector styles.

Is relatively immune to the effects of circuit topology.

This technique does have some limitations:

Requires a leadframe-type package. Device package types such as BGA, PGA or COB have limited internal lead surface area and as such are not generally suitable for the capacitive test method.

Cannot operate in the presence of electrostatic shields. Any conducting surface such as a metal lid or heat spreader will significantly attenuate the capacitive measurement and prevent the technique from operating reliably.

Does not verify other process defects such as reversed or rotated ICs. Generally, the capacitive technique cannot detect that the wrong device was installed. By its very nature, this technique cannot even tell if the IC die is present since it is measuring the leadframe’s capacitance.

The use of an external sensor plate requires clearance above the device being tested as well as some provision in the test fixture to mount the sensor plate. These will generally add significant cost to the test fixture and increase the overall running cost.

A single open fault on multiple pins tied together externally, such as power and ground pins, may not be detectable.

Other vectorless techniques have been developed. These include Hall-effect probing and a method to examine the expected beta of the transistor found by the two ESD protection diodes on the device pin.

Vectorless Test Strategy

Each vectorless method provides substantial fault coverage for many–but not all–of the faults found in today’s boards (Table 1). Providing the highest fault coverage at the optimal cost requires proper use of each vectorless test method as well as the occasional use of traditional test vectors.

Because analog junction test is the easiest and least expensive to apply, it should be viewed as the preferred technique and chosen when possible. RF magnetic induction test is the next choice for devices that cannot be tested using the analog technique.

Finally, capacitive coupling is used to test connectors and sockets. If a part will not yield to any of these, other methods such as vectors and boundary scan should be employed.

If the target device has significant faults due to device programming errors, such as EEPROM or ROM, then the use of test vectors must be considered first since this technique can detect such faults. Another issue to consider is the availability of physical access to the individual test nets. The use of boundary scan may be the only way to provide comprehensive test coverage for high-density board designs.

Conclusion

The use of vectorless testing continues to grow in both popularity and in the variety of available test technologies.

Vectorless test is clearly becoming a major and, potentially, the predominant test method for future SMT boards. Vectorless tools offer improvements in programming time, test coverage, cost and execution speed. However, no single technique can cover the total variety of defect categories in today’s PCB fault spectrum.

All three techniques are needed to achieve the fault coverage associated with vector testing. Together, they can provide comprehensive fault coverage over the entire SMT process fault spectrum and across different device types, package types and circuit configurations.

About the Author

Craig T. Pynn is the Marketing Manager at Teradyne. He has published numerous technical articles and papers on board test and is the author of two books. Mr. Pynn holds a B.S.E.E. degree from MIT and an M.B.A. degree from the University of California. Teradyne, Inc,. Assembly Test Division, 2625 Shadelands Dr., Walnut Creek, CA 94598, (510) 932-6900.

Board ATE

Board Test

Analog

Junction

RF Magnetic

Induction

Capacitive

Coupling

Fault Class

Opens