We’ve all heard it. We’ve all said it. We’ve all come to accept it as one of the imperative IC manufacturing missions of the ’90s. And yet today’s semiconductor production manager faces the dilemma of whether to systematically reduce the cost of test to improve profitability, or to just get the current quarter’s devices tested and shipped on time.
True, management may profess the desire to reduce test costs by optimizing the costs of ownership, but when the rubber meets the road, shipping parts usually takes priority and this dictates that there be no change in the installed base of testers. The risks of adopting a new, more cost-effective test platform or even implementing new test methods may be too high and the downtime unacceptable.
The predicament of having insufficient time to implement an effective test cost-reduction plan might be avoided if reducing the cost of test was approached not as a tester decision, but instead as a testing process decision. In terms of devices shipped, the testing process includes tester reliability, prober or handler setup times, throughput of the test cell and product yield. In terms of cost of ownership, the testing process is a function of equipment depreciation, ease of use, floor space, utilities and service.
The solution to the dilemma of pursuing methodical cost reduction vs reacting to shipment goals lies in standardization, such as that being driven by SEMATECH. As ATE companies develop interface standards and provide universalized turnkey solutions, test efficiencies will improve.
By utilizing technologies which lower the manufacturing cost of the tester and reduce facility requirements, ATE providers can improve the cost of ownership for the customer without cannibalizing their own margins. For example, performance testing, or at-speed testing, should be performed at probe rather than at final test, driving fallout earlier in the process.
Another example lies in the integration of post-package testing, lead scanning and marking. Although ATE vendors have considered such integration, few to none have acted and so these typically remain as separate operations on the manufacturing floor. The technology certainly exists to combine these operations, and doing so makes the process more efficient and less expensive.
The computer industry has historically responded well to the demand for an increase in speed and performance and a reduction in physical size and power requirement. Such progress has been achieved with the full expectation of compatibility with older systems.
This is what scaling is all about, and the ATE industry has been slow to respond. The objective of every tester manufacturer should be zero-footprint testers so they can fit on the engineer’s desk, perch on the prober or be built into the handler. This will go a long way in providing for a turnkey environment as well as making the tester transparent to manufacturing.
And what about newer test methodologies? ATE manufacturers are in the best position to develop and integrate compatible, cost-effective solutions for BIST, SCAN and at-speed testing to improve test coverage at probe. Eventually, even burn-in could be performed at probe.
For all of this to happen, the ATE manufacturers must not let the customer dictate test methodologies, but each must work together to develop effective levels of test. Correlation between testers and common hardware interfaces will be essential. In fact, different tester competitors could eventually second source each other. As Intel’s Craig Barrett recently stated, the key to the industry’s success lies in enlarging the pie rather than fighting for market share.
Jim Healy
CEO and President
Credence Systems Corp.
Fremont, CA
Copyright 1995 Nelson Publishing Inc.
September 1995
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