COS Testing Expands Charge Monitoring, Reduces Costs

As performance levels for microprocessors continue to increase, critical chip dimensions will have to shrink. That means companies will be looking harder for new process

control improvements to achieve tighter monitoring and control of wafer contamination.

A new method does more testing more quickly—and at a lower cost. Corona oxide semiconductor (COS) testing, an approach created at IBM and fully developed by Keithley Instruments, combines multiple noncontact test techniques in a single system that is fast enough to make increased sampling economically feasible.

The goals for higher performance were identified in the National Technology Roadmap for Semiconductors, published by the Semiconductor Industry Association. The document called for devices to be operating at on-chip frequencies of 450 MHz for high-performance microprocessors and 200 MHz for volume microprocessors just three years from now.

To achieve such levels, we will need transistor channel lengths in the range of 0.5 to 0.25 µm, junction depths as shallow as 0.1 µm, and gate oxides 40 to 60 Å thick. At the same time, operating voltages will have to be 2.5 V or lower, and threshold voltage (Vt) variations must be reduced to less than 50 mV.

These new targets mean that charge monitoring will become even more important due to increased sensitivity to electrically active contaminants.

Ideally, in a perfectly formed oxide and interface there would be no contamination charges present. In practice, some level of charge is unavoidable and undesirable, because such charges affect the electrical performance of the device. Figure 1 shows the charges which make up the net charge associated with the oxide system.

Monitoring electrical charges during semiconductor wafer processing has been time-consuming and expensive, but essential to ensure quality. It is estimated that a 0.35-µm fabrication facility with 5,000 wafer starts per week now spends from $500,000 to more than $1 million annually on charge monitoring.

C-V Testing

In today’s fabrication facilities, capacitance-voltage (C-V) monitors are typically used to test for charge contamination from diffusion and etching processes and from plasma-based equipment. C-V testing uses prime grade test wafers, run either with a batch of product wafers or as part of a test run to monitor equipment performance. Preparation of these wafers requires additional processing to apply conductive contacts needed for testing, which adds cost and lengthens the process qualification cycle by anywhere from a full shift to several days.¹

Despite the inconvenience and cost, semiconductor manufacturers continue to invest in charge monitoring because variations in electrical performance due to charge contamination affect device yield and reliability. Still, the benefits of monitoring must be balanced against the time and expense involved.

Charge monitor runs are usually scheduled weekly. In a worst-case scenario, this puts a week’s worth of wafers at risk for each piece of process equipment being monitored. It is not uncommon for a fabrication facility (fab) to lose up to a million dollars in potential revenue because a production lot with a charge-related problem was scrapped. An investment in metrology equipment for charge monitoring has the potential for a big payback.

COS Technique

Unlike C-V testing, COS measurements are made without touching the wafer or changing its physical properties and can be completed in a matter of minutes. COS test wafers require little preparation time–there is no need to add electrical contacts–and can be easily recycled for future use.

COS testing not only performs the same flatband measurement usually quantified with C-V tests, but also provides measurements of mobile charge, near-surface doping, effective electrical oxide thickness, static charge maps and net charge maps. And it does so in considerably less time: With complete automation, process monitors can be completed in hours instead of days, as is common with C-V testing.

The COS technique applies a bias to the oxide through the application of a precisely controlled, low-energy corona. This corona bias is applied by charging air molecules and directing them toward the oxide surface. Since this occurs in air, the charged ions reach the surface of the oxide with a very short mean free path (less than 0.1 µm), so there isn’t enough kinetic energy to penetrate the oxide layer.

After applying the corona bias, the COS technique uses a modulated light source to create a time-varying surface photo voltage signal, which is measured with a vibrating Kelvin probe. Figure 2 shows a block diagram of the equipment. By combining these functions, the COS technique can trace bias vs the surface potential, which produces a Q-V/SPV curve. From this data, it is possible to extract flatband voltage (V_fb), an important indicator of oxide integrity, directly from the measurements (Figure 3).

Since COS techniques correlate so closely with C-V results, there is significant value in using existing analysis tools and C-V history with COS techniques. Converting COS-generated

dQ

Q-V data to C-V is straightforward, given that C = dV. The resulting data can be used in any C-V analysis utilizing low frequency or quasistatic C-V data. You don’t have to learn new trending and analysis techniques to effectively use COS process monitoring equipment.

Benefits/Savings

While COS offers technical improvements in process monitoring and understanding, you still need to justify new equipment and processes on an economic basis. This requires an economic model for metrology equipment purchases.

SEMATECH has a model of the cost of ownership (COO) for processing equipment and is developing a metrology model. Currently, the metrology model consists of two parts, the first involving cost of equipment operation and the second addressing the impact of metrology information. These parts are expressed as two terms in an ROI equation for metrology equipment:

Benefit_Product + Benefit_Process

ROI = _____________________

COO_Metrology

The first term quantifies the benefits of replacing current methods of monitoring, while the second attempts to put an economic value on information about the process.

Product-related benefits coming from replacement of current methods include:

Reduced cost of testing.

Reduced cost of material preparation for testing.

Reduced cost of test material.

Increased availability of production processing equipment.

Greater timeliness of data collection.

The application of metrology provides information that increases understanding of what is going on in manufacturing processes. This information can be used to:

Improve sampling methods.

Implement tighter process control to reduce product loss.

Speed qualification of a new process.

Reduce costs by not shipping bad product.

Reduce costs by not rejecting good product.

For example, consider the cost savings possible by replacing traditional C-V test equipment with COS technology. We’ll limit the evaluation to the non-contacting nature of COS and the cost savings achieved by eliminating processes needed to apply conductive C-V dots.

Our model assumes a typical fab running two C-V monitor wafers on each piece of equipment an average of once per week. A 0.35 µm fab with 5,000 wafer starts per week will typically monitor approximately 62 pieces of equipment. If the equipment operates 50 weeks per year, this fab will need to process and test 6,200 C-V wafers each year.

The model also assumes that the lithography method is used to apply the conductive dot pattern to C-V test wafers, as opposed to using a metal mask, which yields less accurate results. Table 1 lists major costs associated with a monitor wafer and its preparation for C-V testing vs COS testing.

The annual equipment qualification C-V testing costs for this fab are: 6,200 wafers/year @ $124/wafer = $768,800/year. With COS technology, the only monitor wafer processing costs are those associated with annealing, testing and a portion of the wafer cost allocated to a specific process run. To test the same 6,200 monitor wafers per year, the cost is $165,850, a savings of $602,950.

While the saving of $602,950 is significant, this model does not include related savings. By eliminating the need to prepare 6,200 C-V test wafers on production equipment, you increase availability of that equipment for revenue-producing production by 1% to 3%. The model also doesn’t attempt to quantify the benefits of not having several days’ worth of material at risk while awaiting C-V test results. Another factor not considered is the quicker availability of equipment. With COS technology, processes can be adjusted and equipment can be brought back on-line to run production material within minutes after completing a test run, instead of requiring shifts or days as with C-V monitoring.

Conclusion

Understanding charges and their sources is becoming more important in modern semiconductor devices as geometries and tolerances shrink. Today’s typical annual expenditure of one-half to more than one million dollars for C-V testing may not provide adequate monitoring and control of charge generation in the future.

COS technology is a solution that not only replaces C-V monitoring at substantially lower cost, but also provides additional information to improve the understanding of production processes.

References

1. D’Elia, M., “Capacitance-Voltage (C-V) Measurements in a Manufacturing Environment,” SEMATECH Technology Transfer Document #93021492A-TRG, SEMATECH, 1993.

2. Dance, D.L., “Cost of Ownership Analysis for Metrology Tools,” SEMATECH, 1994.

3. Verkuil, R.L., and Fung, M.S., “A Contactless Alternative to MOS Charge Measurements by Means of a Corona-Oxide-Semiconductor (COS) Technique,” Spring Electrochemical Society Meeting, Abstract 169, 1988.

About the Author

Michael A. Peters is a marketing manager for the Process Monitoring Group of Keithley Instruments, Inc. He has 10 years of experience with Keithley in applications, sales and marketing of in-line test equipment. Prior to Keithley, he worked as an electrical test manager at Intel Corp. Mr. Peters received a B.S.E.E. from the University of Cincinnati and an M.B.A. from Kent State University. Keithley Instruments, Inc., 28775 Aurora Rd., Cleveland, OH 44139-1891, (216) 248-0400.

ATE

Legend for Figure 1

Q_net

: net change

Q_surface

: charge due to electrically charged surface contaminants or static charge

Q_ot

: charge trapped in the oxide, often due to processing damage

Q_fixed

: non-transferable charges trapped at the Si/SiO₂ interface, caused by dangling silicon bonds formed during the oxidation process

Q_it

: trapped charge that may be transferred between the Si/SiO₂ interface and the bulk silicon, depending upon bias conditions

Q_m

: mobile charge, usually due to sodium or potassium contamination

Table 1

C-V COS

Step Cost Cost

Pre-Clean 6.00

Al Deposition 11.00

Litho Step 9.00

Etch 6.00

Clean 6.00

Anneal 3.00 3.00

Test* 8.00 20.00

Wafer Cost (8″) 75.00 3.75**

Total ($/Wafer) 124.00 $26.75

* Based on equipment depreciation

** Wafer cost = $75/wafer, amortized over a minimum of 20 process monitor runs

Copyright 1995 Nelson Publishing Inc.

September 1995