The Ins and Outs of Parallel IC Handlers

Test costs are becoming an ever-larger percentage of the cost of an IC. In fact, the cost of test could be as much as 30% of the cost of an IC. The cost of test includes not only the tester, but also the handler. And robotic handlers—today’s handler of choice for many applications—can cost a million dollars or more.

One of the most common techniques to reduce the cost of test is parallel test. But first you need a handler that can accommodate two or more parts at the same time.

Two types of parallel handlers are on the market today. The first type handles two to four parts simultaneously. These systems test complex logic devices such as microcontrollers.

The second type of parallel handler accommodates anywhere from 16 to 32 devices simultaneously. These systems test DRAMs or other memory parts.

By testing two or more components at the same time, you effectively reduce the test time per component. Lower test times mean higher throughput.

Parallel test makes better use of tester resources, meaning you need less equipment to test the same volume of parts. This is important because tester resources are frequently the most underutilized of an IC fab’s capital assets. Better use of tester resources translates into a higher return on investment. Figure 1 shows how throughput increases with parallel testing.

The applications that benefit most from parallel test are those where test times are long in comparison to the prober/handler shuttle time. Devices of this type include microcontrollers and memory devices. On the other hand, test times for simpler logic devices are usually much shorter and the benefits of using parallel test are not as high.

When selecting a handler for parallel test operation, there are several things that must be considered to achieve the highest throughput. The most important specifications are index time, sort time and load time. If the load time and sort time are shorter than the test time, throughput will be:


throughput = ——————————– x # of devices tested in parallel

index time + test time

When the load time or sort time is longer than the test time, the throughput will be:


throughput = ——————————– x # of devices tested in parallel

sort time or load time

If the index time and test times are dwarfed by the sort times, then throughput will also be low. This is especially true when testing parts that may be sorted according to clock speed or power consumption, such as microcontrollers and DRAMs. For example, a handler may have to sort these parts into eight bins, and sort times may be in the range of four to five seconds. In this application, choosing a handler solely because it has a low index time doesn’t make sense.

The way you load and unload trays and magazines will also affect throughput. Tray loading is still a manual operation in most facilities, and because of this, slows throughput.

For the highest possible throughput, make sure the handler is as easy as possible to load and unload. To accomplish this, the handler should conform to the standard Safety Guidelines for Semiconductor Manufacturing Equipment.1

Also important is the bandwidth of the test-fixture interface. Many of today’s digital components run at clock speeds of hundreds of megahertz, and digital signals contain frequency components many times the clock frequency. If the fixture must maintain the fidelity of the test signals, it must have a bandwidth in the gigahertz range. Fixtures with a lower bandwidth will degrade test signals, increasing the number of devices that must be retested and lowering the overall throughput of the system.

In some applications, the ability to quickly change the test-fixture interface can be important, too. If you must spend much time changing the test fixture, your throughput will suffer.

Another important consideration is the way the handler accommodates surface-mount devices. Many pick-and-place handlers pick a device off a tray and insert it into a test socket vertically. This approach can damage devices or bend leads if the device is even slightly misaligned.

Other handlers pick up a device and present it to the test site horizontally. Handlers that use this approach actually release the part and allow it to drop several millimeters into a self-aligning socket. After the part is properly aligned, the handler pushes the device into the socket to make good contact. This method reduces the number of damaged devices and the number that must be retested, increasing the throughput of the whole system.

Finally, let’s take a look at the issue of factory automation. The back end of an IC process is much less automated than the front end, primarily because the transport media, such as trays and magazines, lack some of the features needed for automated handling at test. For example, currently there is no way to mark a tray or magazine with pass/fail information or device speed information. Without this information, it is virtually impossible for factory-automation systems to correctly identify and handle the parts.

Fortunately, industry groups are turning their attention to the problem of factory automation, and representatives of interested companies will meet soon to discuss these issues. Although a standard will take some time to develop, it is encouraging that the industry is beginning to work on these problems. The end result should be higher test throughput.


1. Safety Guidelines for Semiconductor Manufacturing Equipment, SEMI S2-93.

Semiconductor Equipment and Materials International, Mountain View, CA, 1993.

About the Author

Katsumoto Hayashi is the Handler Product Manager at Advantest America. He is a graduate of Japan’s Aichi Institute and has worked in the handler industry for 14 years. Advantest America, 1100 Busch Parkway, Buffalo Grove, IL 60089, (847) 634-2552.

Copyright 1996 Nelson Publishing Inc.

May 1996

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