Integration and Synchronization in Complex-Digital Mixed-Signal Testing
As semiconductor technology evolves to increasing levels of integration, a new class of devices—complex digital mixed-signal semiconductors—is emerging. These devices have a high degree of digital complexity and integrate analog functionality on the same IC.
Device categories include multimedia graphics controllers and video encoders/decoders with on-board RAMDACs, communications controllers with on-board transceivers, and digital signal processors (DSP) with codec functionality integrated onto the same monolithic IC. The integration and synchronization of any type of mixed-signal test equipment impact the performance, manufacturability and test-development time. The result is a theoretical framework, based on four classes of data present during testing of complex digital mixed-signal devices, that test engineers can use to make systematic decisions about a test plan.
Four Classes of Data
In a very real sense, complex digital mixed-signal testing is an extension of digital logic testing. Digital logic testing involves one type of data: digital data. When logic testing is extended to mixed-signal, it becomes worthwhile to distinguish between the logical type of the data and the form that the data takes during a test.
The form of the data is its actual physical characteristics—the physical interface that must be made to access or generate the data. The type of the data refers to how it is created or processed; that is, how the data is viewed logically. The class of data used in digital logic testing is the digital data type in digital form (DD data).
Mixed-signal testing adds three classes of data: analog data in digital form (AD data), digital data in analog form (DA data) and analog data in analog form (AA data) (Table 1). An example of AD data is the output from an analog-to-digital converter (ADC). The ADC produces digital codes that logically represent an analog signal. The type of the data—how it is logically understood and processed during the test—is analog. The actual physical form that the data takes during the test is digital. The input to a digital-to-analog converter (DAC) is also AD data.
The input of an ADC and the output of a DAC provide good examples of AA data. In both cases, we have logically analog signals, and the physical form they take during the test is time-varying analog voltages or currents.
DA data is the class of data present on the analog side of digital communications transceivers. A fast Ethernet line-driver output drives digital information, information that is physically in an analog form. This is true for the end application— the data is digital and it is transmitted physically in an analog form—but it is not always true during testing.
If the transceiver driver is being tested for overshoot, settling time or some other analog parameter, the output of the driver is actually AA data. For the purposes of the test, we are interested in performing an analog analysis of the data physically in analog form.
At a pedantic level, it is true that all electronic signals are physically analog but the physical form under discussion refers to the kind of interface that is made to a particular signal. If a digital interface is required to connect the tester to the DUT, the data is in digital form. If an analog interface is needed, the data is in analog form. These distinctions become very important when designing a mixed-signal test system, whether that system is custom or is an application developed for commercial ATE.
The Impact of Data Classification
Why does all of this matter? The basic structure of a mixed-signal test is similar to that of a logic test: the device is stimulated, the device response is captured and the results of the test are determined from the response. By classifying the data, we determine the appropriate instrumentation to use and how to orchestrate its use.
A well-designed mixed-signal test setup deals with each class of data present during the test in an integrated and synchronized fashion. Integration and synchronization have a very specific meaning in mixed-signal tester architecture. They refer to mapping data-type instruments to data-form instruments in space and time—the where and the when.
During the execution of a test, the type of the data determines the instrumentation needed to create the stimulus and analyze the response. D-type data is created by a digital simulator, stored in a digital sequencing memory and compared to expect data from a digital memory. A-type data is usually created and analyzed using DSP techniques.
The form of the data determines the instrumentation required to physically deliver the stimulus to the device and to physically capture the response. Digital drivers/comparators are used for D-form data, while digital-to-analog and analog-to-digital conversion interface to A-form data. A test system that does not allow you to program data type and data form independently will be much more difficult to use than a system that provides this independence.
Along with the data classifications, you must physically distinguish between stimulus and response. As a result, an ideal mixed-signal test system has eight independent functional blocks (Table 2).
Now the typical mixed-signal test involves more than one class of data simultaneously and can involve all classes of data at once. For example, when an ADC is tested, a digital pattern stimulates the digital portion of the IC and compares the device response to expected values (DD data). An analog stimulus is generated at the analog input of the device (AA data). An analog waveform coming out of the device in digital form (AD data) is captured and analyzed to produce the mixed-signal test result.
The AD data is often present on a bus that switches on the fly between AD data and DD data. All of these activities must occur in a carefully orchestrated and synchronized operation.
In the ideal case, the instruments that determine the data type, the sequencers and DSP can be arbitrarily mapped in space and time to the instruments that determine the physical form of the data—the analog and digital pin electronics (Figure 1).
Although the treatment of digital drive and digital compare as separate functions may seem unusual, such “flyby” testers have been constructed. As with most transitions from theory to practice, there are trade-offs. Although a flyby tester has zero-effective round-trip-delay for I/O pins (one of the advantages of instrument independence), the three-way connection produces a complex transmission-line problem that more common integrated digital I/O pins do not have. In the analog case, I/O pins are uncommon, especially at transmission-line frequencies, so using separate instruments for input and output makes test development easier.
Figure 1 shows a basic tester architecture to support a single mixed-signal test. Additional channels, or complete sets of analog or digital resources, increase the number of tests that can be performed in parallel. For example, a system with two sets of analog resources could easily test both the ADC and the DAC inside a codec simultaneously. A practical mixed-signal tester architecture with multiple analog channels is shown in Figure 2.
Synchronization/Integration Functions
Both synchronization and integration are important with respect to the eight basic modules within a mixed-signal tester. Many specific functions must be considered as part of the design of a mixed-signal test application for complex digital mixed-signal devices. These functions break out roughly into sequencing and clocking categories.
Data-Sequencing Functions
Data-sequencing instruments (data type) should be independent of instruments that interface to the device pins (data form). The capability to map analog sequencers to standard digital pins for specified test vectors, and to single-step the analog sequencers from particular test vectors provides the control necessary to logically separate AD data from DD data.
Triggers for starting and stopping sequencers should take place on a global synchronization bus, compensated for pipeline delays. Analog sequencers should process formatted data on the fly, such as serial or multiplexed data. Then, digital pre-processing and post-processing of data by the DSP are not required and memory is used efficiently.
Without these functions, several problems can occur. Complex pre-processing or post-processing of data may be necessary to perform the test because the instruments themselves do not keep analog information separate from digital information. Instruments may be required to perform functions for which they are not logically designed. For example, the DSP may be required to compare digital expect data to device-response data.
System resources may be used very inefficiently, and there may not be enough system resources to run the test program without reloading memories for each device. Any test setup that provides on-the-fly switching between AD data and DD data will provide significantly faster test development, much more efficient use of resources, and a more logical.
Clocking Functions
All clocks should be independent and variable, so that frequency relationships between the analog and digital instruments can be arbitrary. This is especially important when testing to standards that specify particular test frequencies. Variable analog clocks are not sufficient in themselves because a required analog frequency might be an integer multiple of device clocks. As a result, a variable digital master clock is also very important.
Dividing these variable clocks from a single high-speed master clock is insufficient because it results in a system where the only frequencies possible are those that result from integer division of the master clock. That, in turn, makes the selection of test frequencies more difficult and constrained. Truly independent clocking can be crucial for many applications and will be much easier to use for application development in general.
While independent variable clocks provide the most flexibility and consequently make test development more productive, they can also introduce problems if the architecture does not provide phase locking and clock resync. With phase locking, all the clocks in the system, while independently programmable, are locked to the same reference to absolute time.
The phase relationship between any two clocks will be the same from system to system and from test to test, irrespective of any absolute frequency errors. This is very important for measurement repeatability and avoidance of frequency leakage.
Resync provides the capability to reset all clocks to zero phase at the beginning of a test. As a test continues, two clocks programmed to different frequencies will, by design, move out of phase. Resyncing these clocks at the beginning of the test ensures that the process is precisely repeatable from one test to another and from one system to another, since all clocks start from zero phase at the beginning of the test.
Conclusion
Mixed-signal testing introduces four classes of data; digital logic testing had only one class of data. The four classes are composed of physical interface (data form) and logical meaning (data type) for both analog and digital information. Separating these four classes into input and output data results in an eight-module model at the heart of an ideal mixed-signal test system.
For a particular mixed-signal test problem, this model can be used to determine where it is important to use independent instruments and what kind of control is required over where and when the instrumentation is used. Failure to consider the data- class question when developing a mixed-signal test plan can result in inefficient use of resources, longer development time and lower test quality.
About the Author
Matthew Freivald is a Product Marketing Manager at Schlumberger ATE. Before joining the company two years ago, he was a Senior Test Development Engineer at National Semiconductor. Mr. Freivald received a B.S. degree in computer engineering from Rochester Institute of Technology and a master’s degree from San Jose State University. Schlumberger ATE, 1601 Technology Dr., San Jose, CA 95110-1397, (408) 437-5276, [email protected].
Sidebar
An Application Example
To test an integrated codec (a device containing both an ADC and a DAC) in a DSP processor (Figure 3), three classes of data are involved:
AA data is present at the output of the DAC and the input of the ADC.
AD data is present at the input of the DAC and the output of the ADC on digital device pins.
DD data is present on the digital pins of the device throughout most of the test except when the AD data is present on those same digital pins.
The need for flexible control and synchronization becomes obvious very quickly. Handling the AD data and DD data can be complex since they can, in some cases, share the same pins at different times during the test.
For this example, suppose that a DSP processor with an on-board codec is tested for signal-to-noise ratio and total harmonic distortion. The AD data for the DAC shares a data bus with DD data during the same test. The data is always in a digital form, but it switches on the fly between the analog and digital type. The AD data for the ADC shares the same bus but uses it at a different time during the test.
Table 3 shows what the test vectors for this device might look like.
It represents the class of data in the digital test vectors presented to the device at time n through time n+5. The class of data determines its source or destination during the execution of a particular test vector.
The data is always on digital pins because it is always in digital form, but it switches on the fly between the analog type and the digital type. On vector n+1, the device is driving physically digital data on its data bus. This data represents an analog signal, the output of the embedded ADC (AD data). It will not be compared with expect data to produce a pass/fail result as DD data would be. It will be transferred by the analog measure sequencer into the DSP for signal processing.
On vector n+4, the digital pins of the data bus must be driven with analog information intended for the input to the embedded DAC, again AD data but driven by the tester instead of the device. This data does not come from digital simulation, but is generated algorithmically by the DSP and passed to the digital pins through the analog source sequencer. In each case, the class of data determines where the data goes and when it goes there—integration and synchronization.
Table 1
Analog Form
Digital Form
Analog Type
AA
• Input to ADC
• Output from DAC
• Input/Output of Analog Amplifier
AD
• Output from ADC
• Input to DAC
Digital Type
DA
• 10 Base-T Ethernet Signal
• Fast Ethernet Signal
• ATM Transceiver Signals
DD
• Microprocessor Address and Control Data
• Digital Test Vectors and Timing from Simulation
Table 2
Functional Block
Stimulus/ Response
Logical Data Type
Physical Data Form
Analog Source Sequencer + DSP
Stimulus
Analog
Analog or Digital
Analog Measure Sequencer + DSP
Response
Analog
Analog or Digital
Digital Drive Sequencer
Stimulus
Digital
Analog or Digital
Digital Compare Sequencer
Response
Digital
Analog or Digital
Analog Source Pin Electronics
Stimulus
Analog or Digital
Analog
Analog Measure Pin Electronics
Response
Analog or Digital
Analog
Digital Drive Pin Electronics
Stimulus
Analog or Digital
Digital
Digital Compare Pin Electronics
Response
Analog or Digital
Digital
Table 3
Vector #
Data Class on the Digital Control Lines
Data Class
on the Address Bus
Data Class on the Data Bus
Data Source/Destination for the Data Bus
n
DD
DD
DD
Digital Sequencer
n+1
DD
DD
AD (Compare)
Analog Measure/ DSP
n+2
DD
DD
DD
Digital Sequencer
n+3
DD
DD
DD
Digital Sequencer
n+4
DD
DD
AD (Drive)
Analog Source Sequencer
n+5
DD
DD
DD
Digital Sequencer
Copyright 1996 Nelson Publishing Inc.
July 1996
|
|