Tektronix Raises the Bar With New Logic-Analyzer Family

You can design and build what you think is the best product around, but will people buy it? That could be a tough question to answer unless you first conduct meaningful market research and find out what users really want and need. Armed with this information, you then design your product accordingly.

Well, the folks at Tektronix did just that and more when they developed their latest instrument—a logic analyzer. Over the last three years, the company conducted extensive market surveys, made copious phone interviews and held numerous focus groups to help identify the problems users experienced with logic analyzers.

A total of 3,500 engineering professionals and experts from around the world took part in the study. Tektronix asked them a number of basic questions, such as what is the primary source of frustration with your present logic analyzer and what is your rationale for buying a new instrument.

What they found is not surprising. The top two complaints with logic analyzers are difficult user interface and instrument setup. In fact, two-thirds of the participants in the phone-interview study cited the user interface as the biggest problem and a quarter of those surveyed said they were dissatisfied because the instrument was too difficult to use or set up.

Additionally, almost a fifth said there were too many connections that had to be made between the instrument and the device under test (DUT). As the reason for buying a new logic analyzer, 39% said they needed more timing resolution, 16% needed more channels and 14% needed deeper memory.

Using the market-research data, Tektronix developed the TLA 700 Series card-modular logic-analyzer family. The series includes color portable and color benchtop mainframes, logic-analyzer modules, digital storage oscilloscope (DSO) modules and the Windows® 95 operating system. All modules and software are fully interchangeable between the portable and benchtop mainframes.

The logic-analyzer modules offer simultaneous 2-GHz timing and 200-MHz state analysis through a single probe, eliminating the need for multiple connections to the circuit under test. There are four logic-analyzer modules in the series offering from 34 to 136 channels per module with 512 kbits of memory per channel. The benchtop mainframe can accommodate up to 680 channels.

To provide improved timing resolution, Tektronix uses an asynchronous digital oversampling technique which is derived from the digital real-time technology featured in the company’s TDS series oscilloscopes. This technique, called MagniVu™, enables the logic-analyzer module to deliver 500-ps timing resolution on all channels (see sidebar).

MagniVu allows you to pinpoint subtle timing problems, such as glitches, noise or transients. The TLA Series can automatically hunt for glitches on each channel. A glitch detector monitors the data; and when a glitch occurs, the detector triggers the analyzer. Also, the logic analyzer can trigger on timing violations, such as setup-and-hold timing faults.

Two DSO modules are also offered in the TLA Series—a two-channel and a four-channel version. The DSOs feature a 5-GS/s single-shot sample rate and a 1-GHz analog bandwidth on all channels. Each channel has a 15k record length.

Connecting logic-analyzer probes to the DUT has never been easy . To help solve this headache, Tektronix designed a new high-density probe to support both high-speed timing and state analysis. The probe is a cable assembly that has 34 signal connections with less than 2.0 pf of capacitive loading per channel. The probe design provides isolation between channels and shielding to prevent outside interference. An integral latching mechanism assures positive connection to the mating connector of the circuit under test.

Tektronix has integrated Windows 95 in both mainframes to provide a user interface that is familiar to most engineering professionals. The user interface includes the Windows 95 toolbar as well as specific logic-analyzer controls and displays. TLA 704 Color Portable Mainframe: $9,000; TLA 711 Color Benchtop Mainframe: $14,000; Logic Analyzer Modules: starting at $5,000; DSO Modules: starting at $10,000, and P6434 High-Density Probe: $995. Tektronix, (800) 426-2200 (press 3, code 1001).

MagniVu

As the speed of digital logic continues to increase, today’s 100-MS/s logic analyzers just cannot keep up. To create a logic analyzer with improved timing resolution across all channels, Tektronix leveraged a technology that has been successfully used in its high-speed portable oscilloscopes. The result is a fast asynchronous oversampling technology, called MagniVu, that enables the TLA 700 Series Logic Analyzer Modules to deliver 500-ps timing resolution on all channels.

MagniVu acquires all input signals including clocks, asynchronously with a full-custom, high-speed digital sampling front end. The 500-ps resolution is achieved using circuitry driven by a 250-MHz clock.

Instead of scaling conventional techniques to gigahertz clock rates which would be extremely expensive, Tektronix started with a slower on-board 250-MHz clock and built a delay chain consisting of eight precisely controlled 500-ps delays to clock a set of eight sampling circuits (see figure). For every 4-ns tick of the 250-MHz clock, eight samples are acquired at 500-ps intervals for each channel, virtually producing 136 bytes of sampled data for each tick. These 136 bytes of sampled data are then processed digitally every 4 ns.

Each consecutive eight bits of oversampled data is loaded in parallel every 4 ns into a shift register that feeds the various processing elements. The external clock channels are processed and used, along with setup-and-hold characteristics specified by the user, to determine which sample from each channel to use for synchronous acquisitions. Selected samples of the data are fed triggering and storage parameters, based on user-defined clocking, to a large memory with 512 kbits per channel.

This large memory, implemented off-chip using common RAM devices, stores data asynchronously acquired at up to 250 MS/s or synchronously acquired at up to 200 MS/s for all channels at all times. The same oversampled data is processed simultaneously to check all channels for transitions, glitches and setup-and-hold time violations.

At the same time, another faster memory, which is implemented on-chip as a custom array, directly stores 2 kbits per channel of the unconditioned stream of data straight from the 2-GHz sampler for each channel. This high-speed memory is large enough to store eight to 50 bus cycles worth of information for today’s leading microprocessors.

So, as the overall state activity is stored in the larger, slower memory, complete timing information is simultaneously directly captured in this faster memory. The result is simultaneous 2-GHz timing and 200-MHz state analysis.

Copyright 1997 Nelson Publishing Inc.

March 1997

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