Boundary scan testing has shown great promise for many years, yet a large part of the electronics industry is not realizing the potential benefits. Why? Because although the benefits clearly outweigh the challenges, implementing boundary scan testing is more difficult than first thought.
Many electronics manufacturers already have embarked on this implementation, but are only in the early stages. Companies migrating from in-circuit testing (ICT) to boundary scan typically go through several stages. Let’s look at what is involved in a potential migration from traditional bed-of-nails ICT to a hybrid boundary scan/ICT method and ultimately to replacing the ICT equipment with low-cost boundary scan test equipment.
Progressive Stages of Boundary Scan Testing
There are four stages of boundary scan testing: single-chip, whole-chain, pin- reduction and whole-board (Figure 1).
Single-Chip Testing
As a first step, test engineers use the boundary scan pins on a large device to create an ICT for that device. Here are some common challenges encountered at this stage:
The designer may have hard-wired the boundary scan control pins to power or ground.
There is a lack of a low-cost single-chip boundary scan tool and not enough experience and knowledge to make a wise purchase of a high-end, whole-board boundary scan test generator.
Constraints imposed by surrounding circuitry on the board often require modification to data files that drive the test generator to make the test work. Modifying these data files is tedious and error-prone, and requires knowledge that the typical test engineer does not have.
Whole-Chain Testing
After the single-chip stage, enterprising test engineers graduate to whole-chain boundary scan testing. Whole-chain testing involves controlling multiple devices from one four-pin boundary scan bus on the board. This stage is much more challenging for several reasons:
Disabling (guarding) is no longer the sole responsibility of the traditional ICT software. The whole-chain boundary scan test generator needs to work with ICT disabling to achieve a reliable test. Some tools have trouble in this area.
The more devices in a chain, the more likely the test will not work on the first try because of an error in input data to the test generator. Our experience indicates that perhaps as many as 20% of boundary scan descriptive language (BSDL) files contain errors. With this error rate, a five-device chain only has a one-in-three chance of working.
A BSDL file describes the boundary scan logic inside a device. BSDL files typically come from IC manufacturers on BBS and WWW sites at no charge, and with big disclaimers regarding accuracy and support.
Debugging chains is tedious at best and very difficult at worst, because of the large number of vectors in the test. Successful debugging requires a good understanding of boundary scan operation, knowledge that few of today’s test engineers have been able to acquire.
Pin-Reduction Testing
After becoming proficient at whole-chain testing, the next step is pin reduction. If all devices on a net contain boundary scan capability, connecting an ICT pin to the net is not necessary. If all of the chips on a board are boundary scannable, large numbers of ICT pins can be eliminated.
Unfortunately, very few boards today contain only boundary scan devices. One solution involves testing non-scan devices through adjacent scan devices. All high-end boundary scan test generators can apply vectors to these non-scan areas of the board via the scan chain, but users must supply the vectors.
Manual vector generation for these non-scan devices is practical only for small devices. Larger devices or clusters of non-scan devices require an additional test-generation tool.
Whole-Board Testing
The next stage is whole-board testing where no ICT is used. Very few companies have reached this stage, so all the challenges are yet unknown.
Relying solely on boundary scan testing places additional burdens on designers to provide extra boundary scan access to nondigital components such as resistors, capacitors and connectors. Alternately, faults involving passive components could be tested on a low-cost manufacturing defects analyzer.
Benefits of Boundary Scan
The benefits of migrating to boundary scan can be many. Boundary scan testing has the potential to reduce test-development costs since high-coverage tests for assembly defects are automatically generated, and to simplify test fixtures with fewer pins. And when used in conjunction with bed-of-nails ICT, fault coverage of assembly defects increases.
When compared to bed-of-nails ICT, boundary scan testing permits higher density board designs. Higher density is a key driver in several industries, such as portable communications and computing, where the potential economic benefit of using boundary scan is huge. The cost of test equipment also is reduced if the in-circuit tester can be replaced by a low-cost boundary scan tester.
Where To Go From Here
Many challenges must be overcome before the great promise of boundary scan testing is realized on a widespread basis. But there is good news. Test engineers are gradually increasing their knowledge, and competition is heating up to provide more effective tools at reasonable prices. Still, more software tools are needed to speed up and simplify the transition to boundary scan testing for test engineers.
About the Author
Peter de Bruyn Kops, president and chief engineer, founded ACUGEN Software in 1986. He has a master’s degree in applied mathematics from Harvard University. ACUGEN Software, 427-3 Amherst St., Suite 391, Nashua, NH 03063, (603) 881-8821.
Why Boundary Scan Isn’t Used Much Yet
Our research has identified several reasons why boundary scan isn’t used much today:
Bugs in BSDLs. BSDL files formally define the structure and parameters of the boundary scan support circuitry inside a device, including the length of the scan chain and order of bits in the scan chain. BSDL files are provided free, but unsupported, by manufacturers of boundary scannable devices. Many of these BSDLs have explicit disclaimers, typically saying that the BSDLs have never been tested.
Lack of automation in some parts of the process, particularly in customizing BSDL files for programmable logic devices.
Few, if any, boards are built entirely with boundary scan devices. This means the board must undergo ICT of the non-boundary scan devices. Once the board is on the in-circuit tester, it usually is easier to stick with the old known testing method (in-circuit) rather than go through the painful process of learning the new (boundary scan).
This “stick to the old method” is particularly appealing in today’s fast-paced, down-sized time-to-market-critical environment but sacrifices the major long-term benefits of boundary scan.
Copyright 1997 Nelson Publishing Inc.
May 1997
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