Matching Data Bus Throughput to Data Acquisition Needs

In the beginning, IBM introduced the PC. The original PC had a 16-bit Intel 8088 processor running at 4.77 MHz, 16k of RAM, two single-sided 160k floppy drives, and no hard drive; ran DOS 1.0, and cost $1,355. That was August 1981.

For data transfer, the PC had a 16-bit internal data bus; but for cost and compatibility reasons, the external data bus was only 8 bits wide. This external data bus, used for adding plug-in boards, is the Industry Standard Architecture (ISA) bus. Originally, it moved 8 bits of data into memory each clock cycle. When the Advanced Technology (AT) appeared three summers later, it had a 16-bit 80286 processor, and the first machines were equipped with a 16-bit version of the ISA bus. So far, so good.

In October 1985, Intel introduced the 80386 chip: the 386DX, the first full 32-bit processor for the PC. Although the first systems using the 386DX did not appear until late 1986 and early 1987, this was big news. For the PC, things were going to be different.

While the 386—optimized for high-speed performance and multitasking—blew away the 8088 and 80286, it also marked the beginning of the end for the ISA bus, although its decline took more than a decade. The ISA bus was well matched to the world of 8- and 16-bit computing, but when the 32-bit chips came along, ISA became just another way to spell bottleneck.

Several successors to ISA appeared—new designs attempting to match bus throughput to the emerging capabilities of the 32-bit processor in the PC market. IBM led with the 16-/32-bit Micro Channel Architecture bus for the PS/2. In 1988, Compaq spearheaded the 16-/32-bit Extended ISA bus. In August 1992, NEC founded the VESA committee to create the 32/64-bit VL (VESA Local) bus.

In mid-1993, pioneered by Intel, the 32-/64-bit Peripheral Component Interconnect (PCI) bus arrived. As the 386 chip did with its predecessors, the PCI bus soon outdistanced its rivals, delivering the best performance and most flexibility on the market, with new capabilities still being tapped today.

The PCI bus eliminated the bottleneck of the ISA bus. It surpassed the capabilities of the ISA bus by delivering:

True processor independence.

Multiprocessor capabilities.

Yet the major, immediate gain was throughput. The ISA bus, with a 16-bit data path and a maximum 8.33-MHz cycle rate, has a maximum theoretical burst throughput of about 16 Mbytes/s, as seen in these calculations (Figure 1):

8.33 MHz × 16 bits = 133.28 Mbits/s

133.28 Mbits/s ÷ 8 = 16.66 Mbytes/s

For an 8-bit ISA bus, this would be reduced by another 50% to a maximum burst throughput of 8.33 MHz. In actual operation, however, wait states, interrupts, and other protocol factors combine to reduce theoretical bandwidth, usually by about 50%. As a result, effective data throughput for an ISA bus can be as low as 1 Mbyte/s.

With the PCI bus, information transfers across the bus at 33 MHz at the full 32-bit data width of the CPU. When the PCI bus is used in conjunction with a 32-bit CPU, the bandwidth is 132 Mbytes/s (Figure 2):

33 MHz × 32 bits = 1,056 Mbits/s

1,056 Mbits/s ÷ 8 = 132 Mbytes/s

Again, while real-life data-transfer speeds are lower, usually in the 80- to 90-Mbytes/s range, this still is more than an order of magnitude greater than possible with the ISA bus.

Onboard Memory

PCI brings high-speed applications to the PC that are impossible or very costly on ISA bus-based computers. For example, the ISA bus requires onboard memory, with the amount depending on speed. For boards with speeds up to 500 kS/s, a buffer of 4 kS is adequate.

While data can transfer in burst across the bus faster than it is being acquired, the interrupt time is nondeterministic. That is, it can take milliseconds to respond to an interrupt, causing data to back up on the board. Once the CPU responds to the board’s need to transfer data, the transfers can happen quickly.

The ISA bus runs out of bandwidth somewhere between 500 kS/s and 1 MS/s, depending on the system involved. Data transfer speeds of 1 MS/s require substantial onboard memory to avoid data loss during wait states.

In high-speed data acquisition and imaging applications, the PCI bus minimizes the need for onboard memory because data transfers across the bus more quickly than is possible with the ISA bus. While PCI does not eliminate the need for onboard memory, it reduces the amount needed. Typically, a PCI bus master transfer involves from 1 to 16 samples of data. This requires some onboard memory to buffer that data; usually 8 kS or less is sufficient.

Master or Slave?

In addition to providing significantly higher bandwidth, both master and slave devices reside on the PCI bus. Basically, a bus master is a board with its own direct memory access (DMA) controller that transfers data independent of the CPU. Bus mastering allows an adapter to hijack the data bus temporarily by bidding for and gaining control of the bus to perform a specific task.

PCI guarantees access to the bus. With PCI’s 3-µs access latency, a bus-master peripheral card takes control of the bus more quickly than was possible with other buses. Yet the PCI specification also limits the time a bus master retains control of the bus.

Other system components are constantly bidding for the bus, and each is assigned a priority: memory refresh first, followed by DMA channels, bus masters in the I/O slots, and the main CPU. For example, a frame grabber operating as a bus master on the PCI bus can get access often enough to transfer images without losing data, in real time, to a monitor for display or to system memory for storage.

PCI bus mastering is implemented on most imaging boards. With a typical video camera sending 30 frames per second, the resulting data streams range from 10 to 40 Mbytes/s. Because the bus has an effective throughput of about 80 Mbytes/s, or 40 MS/s in data acquisition, it is more than adequate for virtually all data acquisition and imaging applications.

If a high-speed application requires bus mastering, one factor to consider is the method used by the board for writing data to memory. Some vendors use a scatter-gather technique, which creates a list of all available open memory to save lookup time. This approach still requires the board to be reprogrammed with a new address to write to the locations on that list.

Data Translation’s approach allocates a block of memory up front, reserved exclusively for data acquisition, and the board’s DMA controller transfers data to this half-megabyte area in the PC’s memory. Using this approach, the DMA controller provides a more efficient operation. Allocating one chunk of memory reduces the overhead on the board in transferring data, and makes board design easier, providing flexibility and cost advantages.

Is Bus-Mastering Essential?

For many data acquisition applications, there is no need for bus mastering. The bandwidth of the PCI bus is more than sufficient to handle data sampling rates upwards of 1,000 kS/s in the slave mode.

In data acquisition and image analysis, if information is coming into the board faster than it can be moved to memory, data can and will be lost. To store the overflow requires onboard memory as a frame buffer, which consumes both real estate on the board and real dollars from a budget.

So while bus mastering can be an appropriate solution for data acquisition applications demanding higher throughput, usually 1 MS/s and above, many data acquisition applications do not require this level of throughput. The PCI bus without bus mastering is a cost-effective solution for the vast majority of data acquisition applications. This is an important consideration in choosing a PCI board for data acquisition.

Selection Criteria

What is the application? Is it a rapid, one-time event requiring multiple input channels, such as monitoring the results of a crash test with air bags exploding at 200 mph, bumpers crumpling, or windows cracking? Or is it slow, over time, such as tracking the performance of a solar cell under varying atmospheric conditions, where temperature changes occur gradually during the course of a day?

Choosing a data acquisition board means finding a product that meets the specific requirements for channel count, sampling throughput, and bit resolution. What combination of board components will best convert such variables as light, pressure, temperature, flow, or sound into measurable, recordable voltages? How much throughput is needed for the ADC input, and how much for the DAC output? Technical considerations include:

ADC, DAC, and digital I/O.

Input ranges (unipolar, bipolar, channel-gain list).

Input types (channels, single-ended/differential input, pseudo-differential, simultaneous sampling).

Accuracy (resolution, effective number of bits, total harmonic distortion).

ADC types.

Analog outputs (independent DACs, settling time, deglitched outputs, reconstruction filters).

Clocks, triggers, counter/timers (oscillator, divider, prescalar, trigger).

Several of these components can be seen in Figure 3, a block diagram of the DT3010 multifunction data acquisition board for the PCI bus.


Yet in high-speed data acquisition applications, the method of data transfer between the data acquisition board and computer memory or the monitor is just as important as the speed of the ADC or DAC. For PC-based data acquisition applications, the basic choice today is between an ISA bus and a PCI bus.

In today’s PC environment, there is one big-picture question to ask before plunging into these nitty-gritty decisions: Is it a new application or an existing one designed for the ISA bus? If the application already is built around the ISA bus and needs replacement or duplication, ISA is the bus of choice. For any new application, PCI is the bus of choice for today and tomorrow.

Beyond the immediate—and significant—throughput gains possible with the PCI bus, its processor independence allows for increased future performance through a processor upgrade, ensuring investment protection. PCI also serves as the model for plug-and-play systems, meaning PCI cards do not have jumpers and switches. Instead, a PCI data acquisition board is configured through software, adding both ease of use and flexibility.

Also, with the move to reduce power requirements in the PC, the future is migrating toward 3.3 V for plug-in boards. While the PCI specification has provisions for 3.3 V, the ISA boards will not provide that migration path.

As new computers appear on the market, the PCI bus already has begun to squeeze out the ISA bus, and this trend only will accelerate. In the not-very-distant future, ISA buses will go the way of leaded gasoline as new PCI models replace them. The large installed base of ISA buses will continue to be useful in low-speed data acquisition applications for many years. But the 32-bit PCI bus, and later perhaps the 64-bit PCI bus, will displace them. New hardware requirements as well as software applications will be written for a 32-bit world, with 64 bits just around the corner.

About the Author

Leslie Logan is the data acquisition product marketing manager at Data Translation. She received B.S.E.E. and M.B.A. degrees from Cornell University, and has been working in the data acquisition and test and measurement industry for 15 years. Data Translation, 100 Locke Dr., Marlboro, MA 01752, (508) 481-3700.

Copyright 1997 Nelson Publishing Inc.

July 1997

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