What You Need to Know About Device TestingESD Association Working Group Members Discuss the Details

Electrostatic discharge (ESD) is so devastating that it can destroy some ICs in a nanosecond and with less than 200 V of charge. To weed out any ESD-susceptible devices and maintain quality levels, manufacturers must test the ESD withstand capabilities of these ICs.

To help them, the Device Testing Working Group of the ESD Association has been addressing these concerns. The results are some detailed test methods recently discussed with EE by two members of the ESD Association Standards Working Group for Device Testing.

Koen Verhaege, technology leader of the Systems and IC Design Laboratory at Sarnoff in Princeton, NJ, is the soft-spoken and erudite coordinator of the ESD Association’s Device Testing Working Group. Leo G. Henry, a reliability engineer at the Corporate Quality Division of Advanced Micro Devices in Sunnyvale, CA, is an energetic and insightful member of this distinguished group.

EE started the interview by asking Mr. Verhaege and Mr. Henry for a brief description of the Human Body Model (HBM) test method. Descriptions of the Machine Model (MM) and the Charged Device Model (CDM) test methods are discussed later in the interview. The conversation included information on combined device test models for broader ESD coverage, proposed changes to the device test standards, and trends in device testing.

EE: Briefly describe the HBM test method and its purpose.

Koen Verhaege: HBM is the most used model in the ESD industry. It’s really the industry standard, the first and oldest device test model.

The history is interesting. Some say it began with the military trying to model the static charge of a standing human. Another explanation comes from the mining industry. For example, a miner can generate a spark that could blow up the mine.

The ESD industry adopted the HBM to characterize an ESD event from a human. It tests the sensitivity of electronic devices to the discharge from a human. The model is comprised of an RC network in series, containing a 100-pF capacitor and a 1,500-W resistor (Figure 1). It is very successful and is still used.

EE: Who needs to use it?

KV: The manufacturers of ICs use the HBM because companies that buy ICs want to know what the ESD withstand voltage or the sensitivity of a part is before purchasing the device. Often, manufacturers ask for a part’s HBM because it is the same as asking for its withstand voltage.

EE: When is it used?

KV: The HBM model is used by engineers to help them design ESD protection for their devices. They test chips until they fail, which yields a sensitivity level or ESD withstand voltage. When the products are released, they already have been qualified according to the withstand voltage classification (Table 1). There is a certain procedure to follow per the ESD Association Standard S5.1-1993 Device Testing Human Body Model to obtain this value.

Some background and testing recommendations on the HBM are available in the 1996 EOS/ESD Symposium Proceedings paper “Recommendations to Further Improvements of HBM ESD Component Level Test Specifications” by K. Verhaege, et al. Another good reference paper on HBM was presented at the 1993 EOS/ESD Symposium Proceedings, “Analysis of HBM ESD Testers and Specifications Using A 4th Order Lumped Element Model” by K. Verhaege, et al.

EE: What test equipment is used?

KV: Typically, automatic test systems are used. There are separate detect and verifier systems. Basically, the device is put in an automated test system and contacted through a relay matrix, voltage zaps are applied, and then I-V current traces are reviewed on an oscilloscope to see if the devices fail. But if you follow the procedure correctly, each time you zap the device, you should take it out and do a full functional test because you also might have core failures or functional failures rather than just I/O failures.

Leo G. Henry: However, each company determines their own acceptable failure level.

EE: Please describe the use and purpose of the MM?

KV: The MM shows the same kind of failures as the HBM for 90% to 95% of the situations. Only in 5% of the cases does it show something different. The MM test method is preferred by the U.S. automotive industry.

The MM originated in Japan as a result of trying to create a worst-case HBM. The Japanese reasoned that, when you are sitting in a chair holding a tool, your capacitance is much higher and your seat resistance is much lower. So they came up with a model that uses a 200-pF capacitor and basically no series resistance (8.5 W ) to discharge through and an inductor of approximately 0.5 µH (Figure 2). It became known as the MM method.

LGH: In the HBM, there is somebody with capacitance touching something and then discharging. With the MM, it is metal-to-metal contact, and there is no resistance. For example, a metal robotic handler can generate a static charge on an IC if it touches the leads of the device.

LGH: The ESD Association’s S5.2-1994 Device Testing: Machine Model is the test standard to use because it is functional and repeatable. It contains the withstand voltage and the classification of the device (Table 2).

The test equipment for the HBM and MM is the same. It’s just the test head that is slightly different for each. The MM version does not have a 1,500-W resistor, but otherwise the test board and socket are the same.

EE: Please describe the CDM.

KV: CDM is an important test method; however, it is less well known and typically not preferred by most industries. A paper from the 1996 EOS/ESD Symposium Proceedings, “Very-Fast Transmission Line Pulsing of Integrated Structures and the Charged Device Model” by H. Gieser and M. Haunschild, provides significant help understanding the CDM.

The Device Test Working Group recently decided to distinguish two CDM test methods. One is for nonsocketed devices and still uses the CDM moniker. The other test method is a work-in-progress that addresses the socketed devices and will be called the socket discharge model or SDM.

EE: What’s the purpose of the CDM?

KV: CDM replicates an event of a device that is charged during the manufacturing process and then rapidly discharged. It is the device itself that contains the charge and then rapidly discharges. The event is a very fast transient best tested by putting a device in the dead-bug mode (leads pointing up) on a field plate, then charging and discharging it.

The SDM was developed when some test manufacturers noticed they could charge and discharge a device similar to the method used in the HBM and MM methods. The device is put in the socket and connected to a high-voltage source and charged and discharged. It’s such a fast and easy test method because you can put any package in the socket.

With the nonsocketed CDM test, a robotic arm contacts the device pins. It creates an air discharge and an arc. However, results can vary if the pins are not exactly aligned before the charge is applied. For example, densely packaged pin-grid array packages with a tremendous number of pins must be precisely aligned for accurate results.

The socketed device relay is very tightly controlled. If you measure pulses on the socketed tester 10 times or 1,000 times, the pulses will look exactly the same. Do that with CDM, and there will likely be a lot of variability. This is especially true when higher voltages are used because the properties change, causing arcing to occur earlier or later than expected.

LGH: There also is the distinction between the two in terms of the failure mode and the difference in waveforms. The failures that occur in the HBM and MM often happen in the protection structure, and the ones for CDM occur in the gate- oxide.

KV: However, I’ve seen parts where the CDM failures occurred in a variety of places on the device. Usually, it was because the ESD protection design was poor. You can have gate-oxide problems that are related to overvoltage. But when a gate oxide burns out, as in the CDM test, it’s because it ionizes and then releases the energy, causing the gate to break.

The equipment for the SDM and the HBM is the same. For the nonsocketed, or what we call CDM, it is different equipment.

Field-induced CDM or direct-charge CDM (Figure 3) can be induced by manipulating a field on the charge plate or connecting the device to a high-voltage source through a series resistance of more than 100 MW . CDM simulates a device such as an IC that picks up charge when it slides down a shipping tube and discharges to ground when it lands on a metal surface.

The ESD Association’s DS5.3-1996 Device Testing: Machine Model is the latest draft test standard available. It provides the withstand voltage and the classification for the device (Table 3).

EE: Can and should the device testing models be used together?

KV: First, you must decide if you have to do all three tests or if it is possible to get sufficient information from just one. ESD is a problem that is caused by a whole spectrum of events. In real life, when you touch your finger to a door knob, it’s not one zap, it can be five zaps. It is consecutive events and different energies.

ESD is displayed as a whole spectrum when you look at the time and amplitude axes. There is one discrete point called HBM, and it has a specific waveform. There also is one discrete point that is CDM and one that is MM. These are just three discrete points that complete the spectrum of possible events that can occur.

Combining HBM and CDM tests replicates about 95% to 99% of all ESD events that can damage a device. Combining MM and CDM tests also replicates the same percentage of events.

HBM and MM, however, seem to replicate many of the same failures. To be safe, combine the HBM or MM with the CDM test method because there are very typical failure signatures that cannot be produced by just one test.

KV: A paper from the 1995 EOS/ESD Symposium Proceedings, “A Comparison of Electrostatic Discharge Models and Failure Signatures For CMOS Integrated Circuit Devices” by Mark Kelly, et al, reviews HBM, MM, and CDM.

Another useful paper from the 1994 International Symposium for Testing and Failure Analysis Proceedings is “EOS and ESD Laboratory Simulations and Signature Analysis of a CMOS Programmable Logic Product” by L.G. Henry, et al. The paper describes a study that simulated electrical overstress and static discharge with several device testing models and developed a catalog of failure signatures.

EE: What is the purpose of the IC device classification?

KV: It tells IC users where and in what class the device falls (Tables 1, 2, and 3). For an HBM test, for example, a classification level <1 kV means you must be very careful not to let static charge the device. You need top-level static control in your factory or you will have many failure problems.

The class lets you know what level of protection is required. For example, the highest classification lets you know that the part can only be touched in a completely ESD-safe area. But when you have a 2-kV classification, you can be a little more relaxed.

The better the ESD control, the more relaxed the work environment. However, it is not necessary and much too expensive to have a world-class, ESD-safe work environment for every class of device.

The classification system helps you compare parts with the same functionality from different manufacturers.

EE: What is the purpose of the most recent draft standard changes?

KV: For HBM, the biggest problem is device qualification time, especially when testing devices with larger pin outs. A paper from the 1996 EOS/ESD Symposium Proceedings, “A Compact Model for the Grounded-Gate nMOS Behavior Under CDM ESD Stress” by K. Verhaege et al, presented a very simple formula that counts the number of zaps that you use in a device qualification test. It can be a large number of zaps. If you use the current standard, some devices take up to two weeks to be fully qualified because they have to be tested to all the classification levels.

The biggest concerns are the need to reduce the qualification test time. The most significant change to the device test standard is lowering the number of zaps required from three per level to one per level. Instead of having a 1-s interval between two zaps, the draft standard reduces it to a minimum of 300 ms.

I believe the time interval can be decreased to 10 ms, but no system is available to perform this rapidly. The paper discussed why and how the decrease in time interval can be achieved.

In the Device HBM Testing Working Group, additional unpublished data proved that testers can go from three zaps to one in 1 s and 300 ms, respectively. Previous testing included three zaps because the testers were not consistent. To ensure that the device was hit, it was done three times.

The other major change is relaxation of the specifications for the capacitance test. More information and examples of test-board capacitance are available in the 1993 EOS/ESD Symposium Proceedings “Analysis of HBM ESD Testers And Specifications Using a 4th Order Lumped Element Model” by K. Verhaege et al. The paper shows an example of why testing board capacitance is important, especially when you must correlate testers.

With high pin-count testers, the test boards get massive and have huge sockets, a lot of wiring, and parasitic capacitance on the board. Right now 40 pF of dynamic parasitic capacitance is allowed. The association will remove that number from the spec because some users try incorrect methods to measure the parasitic test board capacitance.

The 1993 paper outlines a procedure about how to measure the dynamic parasitic test board capacitance. But the general message is: don’t bother. Look at the specs. They were written to control the tester. If the equipment is within the specification limit, the parasitic capacitance is controlled.

The standards for the HBM and the MM require that you measure a pulse through a 0-W load and a 500-W load. The old military standard used only a 0-W load, and it led to many problems.

The 0-W load shunted the capacitor, preventing the observation of the parasitic capacitance. The 500-W resistor load allows you to see the influence of the parasitic board capacitance in the waveform. The parasitic board capacitance is seen in the rise time across the 500-W resistor as well as in the resistor’s peak current. The Device Testing Working Group relaxed the maximum rise time specification from 20 ns to 25 ns.

KV: This idea and the effects of the rise time are explained in the 1996 EOS/ESD Symposium Proceedings paper “Recommendations to Further Improvements of HBM ESD Component Level Test Specifications.” It provides tables and graphs that explain the effects. The change in the standard allows manufacturers to build 512-pin-count testers that meet the specification. But the Device Testing Working Group was careful not to relax the requirements too much because that would cause tester-correlation problems.

EE: What are the trends in device testing?

LGH: The separation of socketed and nonsocketed device testing and the new SDM are the predominant trends.

KV: Wafer-level testing is another trend. Trying to do package-level testing at the wafer level is important because it cuts the time to market. Plus there is a trend toward what generally is called square-pulse testing. The most popular form of this is transmission-line pulse testing or TLP.

In the TLP test, you apply a short square pulse to the device, measure the current and voltage, extract one data point, and measure the point.

LGH: It is limited, however, to a transmission line that you discharge because you can get a square pulse at the transmission line after it is charged up.

KV: An important paper about TLP was presented at the 1985 EOS/ESD Symposium by Tim Maloney and Neeraj Khurana, “Transmission Line Pulsing Techniques for Circuit Modeling of ESD Phenomena.”

Most people use the TLP test method. However, you can use a pulse generator to do repetitive pulses at a slow rate and measure the current and voltage. New products for square pulse testing were shown at the 1997 EOS/ESD Symposium exhibits, and they will advance the capabilities of TLP testing.

Table 1