The number of microcontrollers and microprocessors found in today’s cars and light trucks is expanding yearly. This proliferation of processors has resulted in increased processing power, additional capabilities, and new problems and opportunities for automotive manufacturers. Since the sum total of the processing power is distributed, a means of communications must be established among the various processors to effectively use them.
This has driven auto manufacturers to implement a computer network within the vehicle. Moving along with these efforts have been the U.S. Environmental Protection Agency (EPA), the California Air Resources Board (CARB), and other government agencies.
Auto manufacturers want a vehicle network that allows different processors to share data and to minimize the size and complexity of the wiring harness. The EPA and CARB see the increased processing power as a way to get the vehicle to self-monitor environmental parameters for compliance.
Initially, each manufacturer developed proprietary architectures and protocols. This strategy was inefficient and extremely costly and presented an impediment to independent vehicle-testing programs. As a result, the various parties collaborated to develop a set of standards to implement and use vehicle-based computer networks, sometimes referred to as multiplex buses.
Activity in the area of vehicle-based networks has increased steadily. Today, numerous standards cover cars and light trucks in the United States alone. Heavy trucks, buses, construction equipment, and farm equipment all have their own families of standards, architectures, and protocols.
Cars and light trucks represent a very large segment of the vehicle market, making them a great concern to the EPA and others. To perform independent vehicle testing, it is desirable and necessary that off-board test computers communicate with vehicle computers to obtain data on configuration, performance, and problems.
A law now requires that every new car and light truck sold in the United States be equipped with and support On-Board Diagnostics, phase 2 (OBD-II). To the vehicle owner, this means there is a standardized diagnostic connector under the dashboard. Through this connector, the vehicle computer or computers must support any one of three designated protocols:
J1850 Variable Pulse Width (VPW).
J1850 Pulse Width Modulation (PWM).
This is minimum-functionality legislation. The OBD-II connector may support more than one protocol and more or different messages, have more than the minimum pins populated, and offer other manufacturer proprietary functions.
This article discusses J1850, the Society of Automotive Engineers (SAE) standard for a medium-speed data communications network in cars and light trucks. Of particular concern are the bottom two layers of the OSI network model: the physical and data-link layers. These layers address wires, definition of data transmission (symbols), voltage levels, and timing (speed).
Two Networks, One Standard
The SAE, working with industry and government, drafted and approved the J1850 specification for a vehicle network. The standard exists in the VPW form and the PWM form. Although the two types are not compatible at the physical layer, they do share some common concepts at the data-link layer. Table 1 provides a brief overview of these two network types.
The J1850 standard defines a set of symbols and how they are used to construct a message on the bus. A symbol conveys a single piece of information. Table 2 provides a listing of the J1850 symbols.
The J1850 bus can exist in one of two states: passive and active. Neither of these states, alone, convey information. But the state of the bus is important to understanding the definitions of the various symbols. The active state is the dominant state.
A passive bus condition exists when no nodes drive the bus. Conversely, a bus is active when one or more nodes drive the bus. Physically, these conditions are different for VPW and PWM networks.
Contention on a J1850 bus is nondestructive. Multiple nodes may begin transmission at the same time. The network design provides that a logic 0 is dominant. Consequently, if multiple nodes begin simultaneous transmission, only the node transmitting a 0 wins and continues with its transmission. All other nodes have lost contention, abort transmission, and continue to receive the message in progress.
VPW Physical Layer
A VPW network consists of a single wire, known as BUS+, referenced to ground. For signal-integrity reasons, a reference ground usually is carried along with BUS+ and is not a current carrying conductor. When in the passive state, BUS+ is at near 0 V. Driven active, the BUS+ line typically is +7 V.
PWM Physical Layer
A PWM network consists of a pair of wires known as BUS+ and BUS- (a balanced signal). In the passive state, the bus voltage is -5 V (measured BUS+ referenced to BUS-). Driven active, the bus is at +5 V. Relative to ground, a bus in the passive state has BUS+ at 0 V and BUS- at +5 V. The active state is reversed. Ground is not used as a reference to determine bus state.
All communications on a J1850 bus are accomplished through the transfer of frames. Each frame is constructed the same ( Figure 1). A frame begins with an SOF symbol, followed by the most significant bit (bit 7) of the first byte of the message. The last byte transmitted is a cyclic redundancy check (CRC). An EOD symbol indicates the end of the data portion.
Following completion of the EOD, a responding node (or nodes) may transmit data. If this occurs, it is an In-Frame Response (IFR). IFRs are not required. An EOF symbol follows the IFR to indicate that the frame is complete. If no IFR data is transmitted by any node, the EOD symbol is stretched into an EOF symbol. This can occur since the EOD and EOF symbols are passive.
Transmission of a subsequent frame can commence only after a mandatory IFS time has expired.
The symbols for the J1850 VPW mode are depicted in Figure 2. The nominal timings for these symbols are presented in Table 3. Note that a symbol is defined by the state of the bus and the time interval between adjacent edges.
Bus speed usually is stated in bits per second and is the inverse of the bit time. In the VPW mode, the time to transmit a single bit may take from 64 µs to 128 µs. As a result, the actual bus speed may vary from 15.625 kbits/s to 7.813 kbits/s. The VPW bus has a nominal bit rate of 10.4 kbits/s.
The symbols for the J1850 PWM mode are depicted in Figure 3. The nominal timings for these symbols are presented in Table 4. A symbol is defined by the width of an active pulse within the time period from one rising edge to the subsequent rising edge. A single-bit time is fixed at 24 µs, resulting in the stated bit rate of 41.6 kbits/s.
J1850 on the Road
At this time, GM and Chrysler have adopted J1850 VPW where it is known as a Class 2 bus. Ford has adopted J1850 PWM, known as the Standard Corporate Protocol.
Although both versions of J1850 share some similarities at the data-link layer, this does not imply anything about the upper layers (message construction or strategy). Only one thing can be stated with certainty: All three implementations have to conform, at the least, to the requirements stated in the OBD-II law and related specifications.
J1850 represents a real first attempt at standardization, but there is room for improvement. The limited bandwidth offered by this standard already is showing signs of strain. Road vehicles with multiple networks and gateways are in the future—and the future is near.
Part 2 of this coverage will address ISO 9141 and 9141-2, the controller area network, and more about OBD-II. The article will appear in a future issue of EE.
About the Author
Michael Riley is a hardware design engineer at Advanced Vehicle Technologies. He has developed several products to support both versions of J1850, ISO 9141, and other automotive-based networks. Advanced Vehicle Technologies, 1509 Manor View Rd., Davidson, MD 21035, (410) 798-4038, www2.ari.net/avt-inc/.