An Evaluation of Multiplexed Analog Digitizer Boards Part 1

How many bits of accuracy does a 16-bit board have on a typical PC? The simple answer is: Sixteen, that’s what the manual says. But the real answer is far more complicated.

So how do you know your board is performing to specification? Is there a simple tool that can analyze the capabilities of data acquisition boards?

The answer is yes. We will present some simple techniques for evaluating the analog input capabilities of the most common type of computer plug-in board used in data acquisition.

Our ultimate goal is two-fold. First, we want to learn how to evaluate boards for the purpose of choosing among competing boards. Secondly, we want to learn what we can expect from a board so we don’t embarrass ourselves by presenting faulty data.

Part 1 of this article addresses the common-mode rejection test. Part 2 will focus on aliasing, settling, and ADC integrity tests.

Typical boards can handle:

16 single-ended (SE) or eight differential channels.

Inputs with ranges up to ±10 V.

Gains between one and a few hundred.

Resolutions up to 16 bits.

Sampling rates of up to a million samples per second.

Not all these features will be available on a given board. The board used for tests in this article is the National Instruments AT-MIO-16XE-10. It is a typical board with 16 SE inputs; an input range of 10 V, either bipolar or unipolar; a 16-bit ADC, and a maximum 100-kHz sampling rate. To acquire the data, we used LabVIEW running under Windows 95 with a 486/66 PC with 32 MB of RAM.

We will not go into detail on the setup, calibration, programming, or operation of the board, the transducers, signal conditioning, or cabling, although these are important considerations in any instrumentation system. We will assume that proper voltages have been brought to the board.

We will use commonly available components to test our boards. These components include a 9-V battery, a 6.3-V center-tapped transformer, a capacitor of about 1 µF, some resistors, and lots of wire. A cable that hooks up to the board and a breakout box with screw terminals to connect the components to the analog inputs can make things easier.

The Test Philosophy

A big problem in evaluating measurements is knowing the true value of the measured parameter. For most of our tests, we will rely on two simple techniques: using a short circuit that we know always is exactly 0 V and measuring a non-zero voltage under different circumstances and comparing the readings.

Even with these simple techniques, we still need to be wary of two potential error sources. First, thermocouple effects can occur if we use different metals at different temperatures to make our short circuits. Second, we can pick up induced voltages and currents if our short circuits travel in the vicinity of high voltages or if they make large loops that can act as transformers and pick up magnetically coupled fields. Consequently, we will make sure that our short circuits are truly short, made out of copper, shielded when possible, and far removed from sources of radiation.

Common-Mode Rejection Tests

Every voltage that we wish to measure actually is the difference between two absolute voltages. This voltage difference is called the normal-mode voltage. The average of the two voltages is called the common-mode voltage. Even if we aren’t aware of this common-mode voltage, it always exists. We always want to reject it; that is, we never want it to influence our measurements. Both the multiplexer and the instrumentation stages of the board contribute to the common-mode rejection.

Our first set of tests will operate the board in its differential input mode. Set up a short circuit on the first channel, making sure that both inputs also are connected to ground. Sample the board at some nominal rate such as 1 kHz for 1 s with a gain of 1 just to make sure you can get a flat waveform near 0 V. When you are sure that everything is working correctly, remove the ground connection from the high and low inputs, leaving them shorted to each other but isolated from everything else.

If you continually sample the waveform, you may observe that the waveform drifts away from zero after several minutes. You can induce this effect by bringing a charged object, such as a comb run through your hair, near but not touching the short circuit.

Figure 1 illustrates a typical result. In all of these figures, time is in seconds and amplitudes are in volts.

Why would we be measuring a 5-V pulse on a short circuit? It seems incredible that the voltage across a short piece of wire could remain at several volts for over one-tenth of a second (Figure 1).

Actually, we have violated our maximum working voltage and sent the instrumentation amplifier into a nonlinear region. The lesson learned here is to make sure that every connection to the analog inputs has an ohmic path to ground and does not exceed the maximum working voltage spec of the board.

The term ohmic path means any conductive path that will allow charges to flow. It could be metallic, as in the case of a ground connection. It could be resistive, as in the case of many types of transducers. It could be a collection of active circuits, as in the case of signal conditioners. Or it even could be a battery as long as one side is grounded.

In some tests, we use a transformer. But if we do not connect some part of the secondary winding to ground, we will violate our rule.

Having learned that lesson, connect the short circuit between the two inputs to the ground reference point on the board and take 100 samples per second with different gains. Figure 2 shows our results with two gains plotted on the same graph. Actually, they were sampled separately and combined on the one graph. The top trace is acquired with a gain of 10 (resolution of 30.5 µV), and the bottom trace is acquired with a gain of 1 (resolution of 305 µV).

Even though we are measuring exactly the same thing in two different ways, we can get two different results. For these two gains, the offset differences are the same at the input to the ADC, since they represent the same raw counts, generally one or two counts below zero.

We cannot actually tell if the error is caused by the ADC or the final stage of the instrumentation amplifier. But either way, there is an uncertainty in all our measurements that includes both a DC and an AC component. If we went to higher gains, we would likely see an increase in the raw noise due to the amplifier stage.

For the next test, make the same measurement at one of the higher gains (say 10) but with the short circuit referenced to +9 V and then to -9 V. Remember that we are measuring the same short circuit; it just has a different common-mode voltage. If your board cannot handle a common-mode voltage this high, substitute a lower voltage. In Figure 3, the top trace was referenced to -9 V, the bottom trace to +9 V.

The vertical scale is different in Figure 3 than in Figure 2, and the top trace in Figure 2 would fit nicely between the two traces in Figure 3. A negative common-mode voltage happens to shift the waveform in the positive direction and vice versa. There is no particular reason why this should be so.

On the next board, it could be a different polarity and a different magnitude. This simply represents the less-than-perfect matching in the voltage followers and the imperfect feedback paths in the gains in the instrumentation amplifier stage. This is a purely DC phenomenon.

We can calculate the DC common-mode rejection ratio (CMRR) by dividing the input common-mode range by the observed measured values. Since we applied +9 V in one case and -9 V in the other, the input range is 18 V. The observed difference in the measured readings is about 100 µV, which gives us a CMRR of about 180,000; or the more usual way of representing it, 105 dB (20 times the log of 180,000).

Now let’s replace the 9-V battery with the 6.3-V transformer. The peak voltage on this AC signal is 6.3 × 1.414, or very nearly 9 V. If your board cannot handle this large a common mode, you will need to use a lower voltage transformer. Sample this signal for one-tenth of a second at a high enough rate so that the 60-Hz common mode will show up clearly.

The peak-to-peak voltage of the unrejected common-mode signal is essentially the same as it was for the DC case; that is, 100 µV. This demonstrates that the CMRR at 60 Hz basically is a DC phenomenon. It is not caused by any dynamic effects—it simply is a result of static imbalances in the instrumentation stage.

The CMRR tends to be relatively constant at different gains. But the effect appears worse at higher gains because it becomes a greater number of counts on the ADC. If your board produces a larger signal in this test than the equivalent result from the previous test, your board has a common-mode rejection that deteriorates quite rapidly as the frequencies increase from DC.

For the next test, we would like to see if there is any difference between the board’s common-mode rejection capability in the differential input mode vs the single-ended (SE) input mode. To do this, reconfigure your board for SE operation with a reference connected to the sense line. You will need to change some jumpers if you cannot do this with software.

Short the SE input to the sense input and connect both of these to the 6.3 VAC that is referenced to ground. Figure 4 indicates that, at 60 Hz, the board is just as good at rejecting common-mode signals in the SE mode as it is in the differential mode.

At higher frequencies, the CMRR gets worse. The instrumentation amplifier is not intended to reject a lot of common-mode noise. It is there just to minimize the effects of differing ground potentials caused by power line-induced ground currents. You should use signal conditioning to reject high-frequency and high-voltage common-mode noise.

The purpose of our next tests is to demonstrate that the CMRR deteriorates at higher frequencies. The ideal way to perform these tests requires a signal generator. But we can still get a subjective lesson of how higher frequencies affect common-mode rejection by using noise generated by our computer’s monitor. This also will alert us to keep our signal wires away from such noise sources.

Here’s how to do it. Remove the transformer used in the previous tests. Tape a long piece of wire along the bottom edge of the monitor’s screen, connect one end to ground through a resistor of about 50 W, and use the other end as the source of the high-frequency noise.

First we want to measure the amplitude of the noise. Connect the source end of the wire to the SE input of a channel with the sense input connected to ground. Sample this at a rate of about 1 kHz for 1 s with the highest gain available. Figure 5 shows the result with our test board at a gain of 100.

Although the waveform in Figure 5 looks like random noise, if we had sampled it slightly differently and zoomed in on it, we might think we were seeing a legitimate signal. To illustrate this, reduce the number of samples so that only one-tenth of a second is displayed, and change the sampling rate until a coherent waveform appears. Figure 6 shows an example at 1,184 S/s.

This waveform actually is taking advantage of a technique for measuring high-frequency repetitive waveforms sampled at rates much lower than the Nyquist criterion, such that the signal aliases down to a lower frequency. The waveform in Figure 6 is a close representation of the actual amplitude and shape of the noise generated by the monitor. But it is displayed at a much lower frequency, and we cannot tell what the actual frequency is.

In other words, Figure 6 indicates that we have a 30-ms pulse repeating every 150 ms but, in reality, it is a much narrower pulse with a much higher repetition rate. We are not interested in knowing the timing of this waveform but how its amplitude will be attenuated by the common-mode rejection of the instrumentation amplifier in the next two tests.

The next test will demonstrate common-mode rejection in the SE mode. Change the connection on the sense input from ground to the SE input.

First we notice that the wave shape in Figure 7 is significantly different from the original shown in Figure 6. But this can be attributed to the same reason why the CMRR deteriorates at high frequencies: The two amplifier paths (the high side and the low side) have different phase shifts and gains at different frequencies and do not subtract equally at all frequencies. Nevertheless, the high-frequency noise has been attenuated from a peak-to-peak of 50 mV to a peak-to-peak of 250 µV that is a ratio of 200, or 46 dB. This is substantially worse than the DC-to-60-Hz CMRR of 105 dB.

Next we want to make the same measurement in the differential mode. Change your board as required to put it in the differential mode and connect both sides of the noise source to the high and low inputs. Figure 8 shows the results for our test board.

Here we see a further decrease in the amplitude of the noise to about 100 µV peak-to-peak, which represents an improvement of the CMRR to 500, or 54 dB. We would have expected the CMRR at high frequencies to be better in the differential mode, due to the better matching of both inputs through the multiplexer, than in the SE mode for which only one input goes through the multiplexer.

Lessons Learned About CMRR

Always make sure each input has an ohmic path to ground and remains within the maximum voltage range allowed.

Never rely on the board to reject common-mode voltages other than the unavoidable caused by power line-induced voltages. Use signal conditioners to reject more serious common-mode voltages (high-voltage and/or high-frequency).

Always use differential-mode inputs except when all signal sources have only low-frequency, common-mode voltages.

Always attempt to eliminate common-mode noise sources rather than use filters or amplifiers to reduce them.

Always test your signals with as many gains as possible to observe the variations.

Stay tuned for Part 2 and the next series of tests.


The authors thank Ed Loewenstein at National Instruments for reviewing this article and making valuable suggestions.


This article was written by the authors as private individuals and not in conjunction with JPL or the U.S. Air Force.

About the Authors

Ed C. Baroth is the technical manager of the Measurement Technology Center at JPL. He holds a bachelor’s degree in mechanical engineering from City College of New York and master’s and doctorate degrees in mechanical engineering from University of California.

George Wells graduated from Cal Poly in 1969 with a B.S. degree in electronic engineering. Since then, he has been involved in analog and digital design for instrumentation systems in the Instrumentation Section at JPL.

Jet Propulsion Laboratory, California Institute of Technology, 4800 Oak Grove Dr., Pasadena, CA 91109, (818) 354-8339, e-mail: [email protected].

Joseph Merrell’s background includes more than 30 years of instrumentation experience with the Air Force Rocket Propulsion Laboratory, in private industry, and currently at the Air Force Research Laboratory. He has a bachelor’s degree in business and a master’s degree in information systems. Air Force Research Laboratory, Edwards Air Force Base, CA.


Copyright 1998 Nelson Publishing Inc.

April 1998

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