Reducing Test Costs for Memory Devices

The increasing size, speed, and complexity of memory devices are good news for customers, but can be challenging issues for manufacturers. Reducing manufacturing costs, especially test costs, is a driving force in the industry. The search for a less expensive test strategy requires an understanding of current test approaches and the potential value of the new massively parallel test systems.

Memory devices continue to quadruple in size every three to four years, significantly increasing the time and the cost of pattern testing. This longer test time due to size is offset somewhat by the increasing device speeds, but only by a small amount. In fact, the faster devices require faster, more expensive testers.

For example, features such as burst mode, bank switching, wide data bus, and latency considerations need to be tested in SDRAMs. Other even more complex devices are on the scene.

Testing Memory Devices

To maximize the value of test, memory devices are burned in by operating at elevated temperatures, typically 125°C to 150° C, and elevated voltages for several hours before testing. Burn-in causes early failures associated with infant mortalities. The burn-in parameters are a function of device type and fabrication methodology and must be carefully chosen to find infant mortalities without damaging the devices.

Following burn-in, the devices are ready for testing. Running a set of pattern tests is essential in verifying the proper operation of each memory cell. Test patterns are run with voltage margins and worst-case timing at typically 70° C, 0° C, and ambient temperatures.

Pattern testing is the most time-consuming part of testing and takes longer for larger devices. The effect of increasing memory sizes on the length of pattern testing is shown in Table 1. It shows the execution times for some commonly used test patterns with three different size memory devices all running at the same test speed.

The increasing test times lead to difficult decisions concerning test time vs adequate testing. The industry already has stopped using several complex test patterns because the test times of those patterns grew exponentially with the memory size.

In addition to the pattern testing, it is necessary to accurately measure the access time and DC parametrics of the device. Generally, these measurements are made at all three temperatures and require high accuracy.

Current Testing Approaches

Burn-In Systems Followed by Device Testers

A very straightforward, but expensive, approach uses dynamic burn-in systems. The dynamic burn-in systems provide the elevated temperatures and voltages for burn-in while exercising the device inputs. These systems have batch sizes in the thousands, but do not test.

Following burn-in, the pattern tests and measurements of access time and DC parametrics are performed with batches of 32 or 64 devices on device testers. These tests and measurements are accomplished at high, low, and ambient temperatures with voltage margins and worst-case timing. Device testers require 30 to 60 minutes to test a batch of 64-Mb DRAMs.

The total cost for testing is dominated by the cost of the device testers. To improve this strategy, you can use less expensive device testers or reduce the amount of testing required.

Burn-In-With-Test Systems Followed by Device Testers

Burn-in-with-test systems move the pattern testing from the small batches of a device tester to the larger batches of a burn-in-with-test system. Because the highly accurate access time and DC parametric measurements are not feasible to perform on hundreds of devices in parallel, burn-in-with-test systems focus on pattern testing.

First, the devices are loaded into the burn-in-with-test system. They are burned in by operating for several hours at elevated temperatures and voltages. Following burn-in, the oven temperature is lowered to about 70° C, and pattern testing with voltage margins is performed.

Then the devices are returned to ambient temperature, retested with voltage margins, and unloaded from the burn-in-with-test system.

Finally, good parts from the burn-in-with-test system are run through a device tester for the remaining tests. This strategy lowers the test cost by reducing the amount of testing performed on the device tester.

Burn-In-With-Test System Limitations

Burn-in-with-test systems have varying degrees of success in performing the pattern testing on large batches. The most significant limitations are:

Inadequate timing resolution at the inputs of the devices.

Large amounts of skew at the inputs of the device.

Slow rise and fall times at the device pins.

Insufficient flexibility in the signal formats.

Poor waveforms.

Inability to test a significant number of devices in parallel.

Inability to test at low temperature.

Most of these limitations adversely affect the capability of burn-in-with-test systems to achieve the high level of correlation with the device tester. Ideally, the burn-in-with-test system and the device tester would find exactly the same failing devices in each of the initial batches of devices. This high degree of correlation would allow the pattern testing to be discontinued on the device tester except for periodic integrity checks.

Massively Parallel Test System Followed by Device Tester

Massively parallel test systems derive their name from having a large capacity and the capability to test a large portion of these devices in parallel. For example, the system shown in Figure 1 can simultaneously test 25% of the 4,096 devices in the system.

To achieve high levels of correlation for today’s production memory devices, a massively parallel test system must achieve at least the following levels of performance:


Resolution is the step size available for adjusting a timing edge. Ten-nanosecond resolution allows the edge to be placed 50 ns or 60 ns or some other time divisible by 10. This resolution is inadequate to place a timing edge at time 62 ns, for example. Experience has shown that today’s production memory devices require the test system to have a resolution of less than 1 ns.


Skew is the variation in the time when an edge occurs at the device due to variations in drivers, transmission lines, and other electronics. Achieving high levels of correlation requires this skew to be no more than ± 1 ns. Care must be taken in the layout of the burn-in board and automatic programmable deskewing to compensate for skew in the drivers and formatters on the driver/receiver board.

Rise and Fall Times

Rise and fall times must be fast; in general, less than 7 ns or 8 ns.

Flexible Timing Formats

Programmable inputs to the device-under-test provide the capability to properly place timed edges such as address, data, RAS, and CAS. Programmability also allows the flexibility to test new part types and modify existing tests as required. Timing on the fly is essential to support changing the timing from cycle to cycle within a test. The increasing complexity of the devices underscores the need for this flexibility.


Clean waveforms without excessive overshoot and undershoot are necessary to properly test the device.

Capacity and Throughput

The optimal number of devices on a burn-in board, one component of system capacity, requires careful consideration. As more devices are added to a burn-in board, each output from the driver board is required to drive more test devices over a longer line. This results in degradation in signal rise time and increased skew. Experience has shown that a 128-device board is a reasonable trade-off for current production memory devices.

The other component of system capacity is the number of burn-in boards. A system with 32 boards, each with 128 devices, has a capacity of 4,096 devices. This is large enough to provide significant cost reduction.

Another consideration is the number of devices simultaneously tested in parallel. A large-capacity system that only tests a small fraction of the devices at one time will require much longer testing times than a system with the same total capacity that tests a large fraction of the devices at the same time.

Test Temperatures

Many burn-in-with-test systems only provide the high and ambient temperatures for testing. The capability to test at low temperature is an important part of moving the pattern testing into the less expensive massively parallel mode. Uniform device testing requires very stable temperatures at each stage of testing and very uniform temperatures throughout the chamber to ensure that each device is tested at the same temperature.

Reduced Test Costs

Figure 2

illustrates the cost savings of a massively parallel test system vs a dynamic burn-in system. The burn-in-with-test systems discussed earlier would fall somewhere between these two techniques depending on the degree of correlation achieved:

Conventional—Dynamic burn-in systems run for eight hours with no testing and then feed devices to device testers for 30 minutes of testing.

Massively Parallel—These systems run for eight hours to perform burn-in. This is followed by pattern testing with accurately timed device inputs. Then the devices are fed to device testers for five minutes of access time and DC parametric measurements.

The costs assume a five-year equipment life and do not include costs such as power or floor space. The cost of testing in the conventional approach is dominated by the time required on the device testers. The massively parallel test systems are more expensive than the dynamic burn-in systems of the conventional approach. This expense is more than offset by the reduction in time required on the device testers.

About the Authors

Harold E. Hamilton is founder and president of Micro Control. He has a B.S.E.E. degree from the University of Nebraska and an M.S.E.E. degree from the University of Minnesota.

Table 1.

Test Pattern


Test Cycle


Total Test Time With Margins


16 Mb


64 Mb


256 Mb







Column Disturb





Surround Disturb





Row Disturb










Sliding Bit





Checkerboard With Pause





Copyright 1998 Nelson Publishing Inc.

Charles H. Morris is a technical writer at Micro Control. He received a B.S.E.E. degree from the Georgia Institute of Technology.

Micro Control, 7956 Main St. N.E., Minneapolis, MN 55432, (800) 328-9923,

April 1998

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