A tool to analyze the capability of a PC-based data acquisition system should be cost-effective and simple to use. What it shouldn’t do is take months to set up and run, a large dollar investment in equipment, a special facility, or an in-depth understanding of programming to accomplish. With all these requirements, we may not be able to analyze all aspects of the board’s capability, but we can address those that contribute most of the impact on capability and error.
Part 1 of this article, in the April 1998 issue of EE, addressed the common-mode rejection tests of the most common type of computer plug-in board used in data acquisition. Part 2 focuses on aliasing and settling tests. Our goal is two-fold:
Learn how to evaluate boards for the purpose of choosing among competing boards.
Learn what we can expect from a board so we do not embarrass ourselves by presenting faulty data.
The Test Philosophy
A big problem in evaluating measurements is knowing the true value of the measured parameter. For most of our tests, we will rely on two simple techniques. The first uses a short circuit that we always know is exactly zero volts. The second technique is to measure a non-zero voltage under different circumstances and then compare the readings.
Even with these simple techniques, we still need to be wary of two potential error sources. Thermocouple effects can occur if we use different metals at different temperatures to make our short circuits. Also, we can pick up induced voltages and currents if our short circuits travel in the vicinity of high voltages or if they make large loops that can act as transformers and pick up magnetically coupled fields. Consequently, we will make sure that our short circuits are truly short, made out of copper, shielded when possible, and far removed from sources of radiation.
The Aliasing Test
In the test setup used in Part 1, we used aliasing to sample a high-frequency repetitive signal at a much lower sampling rate. That is a legitimate thing to do when we know a priori what the frequency of the signal is. But when we do not know the frequency components of our measured signal and we want assurance that high-frequency components are not being aliased down, there is a very simple technique to use.
For example, suppose that we observed the signal in Figure 1 on a channel for which we did not expect such a waveform. Then, we sampled the signal at a slightly different rate and observed whether the measured signal remains the same or changes dramatically. Figure 2 is the same signal as in Figure 1, but it is sampled at 1,183 Hz instead of 1,184 Hz.
In addition to this slight change in the sampling rate indicating a pulse repetition rate four times higher, the shape of the waveform appears to have inverted. This is a result of the way aliasing works and provides the proof we need that the signal is suspect. In such a circumstance, find the source of the high frequency and eliminate it if possible or filter it out, which cannot happen here because it is common-mode. If all else fails, ignore it.
Lessons Learned About Aliasing
Sample your signals well above the Nyquist rate (twice the highest frequency component), unless you have a priori knowledge of the signal.
Use good anti-aliasing filters whenever you need to get rid of high-frequency components in your signals.
Remove the source of any high-frequency interference that may creep into your system through common-mode because it cannot be filtered out.
Sample your test setups at different rates to see if high frequencies are aliasing down.
The Settling Tests
Settling time is specifically important because the instrumentation amplifier must rapidly switch between widely varying voltages from multiple sources switched by the multiplexer. Relatively high-source impedances exacerbate the problem, so we will take this into account in our tests. We will perform our tests in the differential mode, although they also can be done in single-ended mode and should be if that is the way you plan to use your board.
We will simulate a finite impedance source by connecting a resistor across the inputs of one channel (referenced to ground) and applying a 6.3-VAC signal to another channel. With a perfect system, when we scan both channels, we would see the 6.3-VAC signal on one trace and zero volts on the other. But instead of a flat trace, we will see some of the 60-Hz AC. This will depend on the scan rate, the gain, and the source impedance.
With so many variables, our tests could go on forever. Instead, we will demonstrate the principles, but you should perform the tests with whatever typical conditions you will be operating your board.
For example, if you are using signal conditioning that produces volt-level signals, you probably will not be concerned with gains other than one or with the effect of high source impedances. Instead, you will focus only on the amount of error as a function of scan rate. This is another reason to use signal conditioning.We performed our tests at three scan rates, starting with the maximum for two channels which, on our board, is 50 kHz, then 40 kHz, and finally 30 kHz. We used three values of source impedance, 0 W, 1,000 W, and 3,000 W, and three gains, one, 10, and 100. The 6.3-V channel always is sampled at a gain of one, and we did not show it on our plots.
Tests were run with 27 combinations of scan rates, source impedances, and gains. But instead of showing 27 variations, we showed just the three gains at the highest scan rate and the largest source impedance.
Figure 3 shows the corruption of a 3,000-
W source impedance by the 6.3-VAC signal at a gain of one, alternately sampled at 50,000 Hz. This is only a four-count variation on the analog-to-digital converter (ADC) even though it is about 1-mV peak-to-peak.
In Figure 4, the gain changed to 10, but this does not increase the noise by a factor of 10. In fact, it reduces the noise by a factor of three or four when considered from a voltage standpoint (relative). But it increases the noise by a factor of three when viewed as the counts on the ADC (absolute). At a gain of 100, the relative noise decreases by less than a factor of two, but the absolute noise increases dramatically (Figure 5).
Table 1 summarizes all 27 cases. For a gain of one, the source impedance has very little influence on the amount of noise. The noise decreases by almost half when slower scan rates are used. The tests were not performed at scan rates lower than 30 kHz since they would show very little further improvement.
At the higher gains, the source impedance can make a big difference in the noise. Increasing the gain by a factor of 100 (at 0
W) only reduces the noise by a factor of 10. This suggests that it is much better to use signal conditioners to amplify signals to volt levels so a gain of one can be used throughout rather than using the board to amplify your signals.
For whatever combination of gains, source impedances, and scan rates you use, choose the corresponding value from the table as an increase in the uncertainty or error range of your measured signals. For example, if you have a source impedance of 1,000
W, a gain of 10, and a scan rate of 40,000, your true signal actually could be 163 µV above or below what you measure, plus all the noise sources determined from the earlier tests. Different channels could have different amounts of noise since they could be sampled with different gains and have different source impedances.
The main cause of the error is the settling time of the instrumentation amplifier. An additional factor called charge injection refers to the stray capacitances that must be charged and discharged through the source impedances when the multiplexer switches between channels. We are not concerned about the mechanisms of the errors since they manifest themselves in similar ways, and we call them settling-time errors.
One thing that we did not test—but which you need to be concerned about in any real application—is the additional capacitance due to long cabling from the transducers or signal conditioners to the analog board. This will cause a similar but greater error to the ones tested here.
Apply this caveat to the test: It really is a worst-case test when a mixture of volt-level signals and millivolt-level signals is scanned together and we look at the errors at the high gain after we sample a high voltage at a low gain.
The charge injection and rescaling of the instrumentation amplifier from a very overloaded condition will result in a larger error than if the gain of the preceding channel was identical to the one for which we are measuring the error. If you want to get more accurate results for the condition of sampling many channels at high gains, create a source of a much lower voltage so that it will result in an almost full-scale output. You can expect an improvement, but it will not be proportional to the gain difference.
Lessons Learned About Settling
Use the lowest possible scan rate consistent with the required bandwidth of your signal sources.
Use the lowest possible gain consistent with the range of your sources and the required resolution.
Use the lowest possible source impedance, which means use good signal conditioning.
Keep your cabling as short as possible.
The ADC Integrity Test
Our last test gives us a vote of confidence for the monotonicity of our ADC, especially in a dynamic sense. Some ADCs, or their associated sample-and-hold circuitry, can test very well at DC. But they can introduce errors for rapidly changing signals, which is what it will see when mulitplexing.
The test is simple. Connect a capacitor (1.5 µF used in this test) in parallel with a 100-k W resistor across the differential inputs of a channel with the low side referenced to ground. Sample the channel at the maximum rate for 1 s in the unipolar mode if your board is capable of this. Apply a 9-V battery across the capacitor/resistor, start the acquisition, and release the battery. The idea is to get a discharge signal like the one that appears in Figure 6.
Although this graph shows a nice RC discharge, we really need to zoom in to look for jaggedness in the waveform. This is likely to appear at places where many bits are changing on the ADC, such as at one-half of full scale or one-quarter or three-quarters of full scale. Figure 7 zooms in around one-half of full scale and shows each sampled point as a dot so we can clearly see them.
A slight jaggedness just below 5 V can be attributed to the normal noise that is present everywhere. The kind of jaggedness we are looking for appears as a notch taken out of the otherwise smooth ramp and will have more than two, maybe as many as five, adjacent samples all at the same voltage.
Scrutinizing the waveform at several other places reveals no candidates. Many other tests can be performed to characterize things such as linearity and accuracy, but these will require more advanced equipment. Our tests are simple ones designed to reveal some of the common pitfalls of using analog boards.
Lessons Learned About ADC Integrity
Test your ADC in a dynamic way, not just static.
Never make assumptions about what the spec sheets do not tell you.
After making all these tests on our board, we need to bring the results together to answer our initial question of how many bits do we really have. The answer will depend on how we are using the board, so we will create two typical scenarios.
The first will be an application using signal conditioning which will allow us to run all channels with a gain of one. It also has less than 1 V of common-mode and is sampled at less than 30 kHz. The second scenario will use the board’s gain of 10 to perform signal conditioning on full-bridge transducers with 5 V of common-mode, scanned at the maximum rate, and have a source impedance of 3,000
For the first scenario, the noise at a gain of one from Figure 8 is -1.5 counts DC and about one count AC p-p. From Figure 9, we note that the common-mode noise will be negligible for two reasons. We are running at one-tenth the gain, so the noise will be less than one count. We also have one-ninth the amplitude, so again the noise will be less than one count. These two factors combine to render the common-mode rejection ratio to be so good that the common-mode noise will be unobservable.
The only other factor is the noise due to the settling error which, according to Table 1, is 588 µV. Since the resolution of the 16-bit board at a gain of one and a range of ±10 V is 305 µV, this is slightly less than two counts p-p. As a result, the maximum AC error from all these sources is three counts p-p, and the DC error is half that. This represents a loss of about two bits (four counts), so it would be legitimate to say our 16-bit board has an accuracy of only 14 bits.
We did not add any error from the ADC integrity test because we did not see any with this board. But if your board shows a notch of any number of counts, add them to the total error.
Remember a couple of things about this analysis. First, it is not really fair to add the maximum errors to come up with a combined error. An rms approach is better. Secondly, we have left out other sources of error, most notably the accuracy of the ADC at voltages other than zero (we have only looked at offset errors), at frequencies other than DC, at temperatures other than nominal, or how the board deteriorates with time.
Even though we characterize our board as having an accuracy of 14 bits, it’s not the same as having a board with only 14 bits. If we were to test that board, it would likely have an accuracy of only 12 bits. We can still use the 16-bit resolution in a relative way.
For the second scenario, we note from Figure 8 that we can again expect the same DC and AC offset error and noise in terms of counts as we did for the gain of one, but we will express these as -46 µV DC and 31 µV p-p AC. The common-mode error due to 5 V (divided by 180,000) is 28 µV. The settling error is 337 µV p-p.
Clearly, the settling error dominates, but let’s assume that the total for all error sources is about 400-µV p-p. Since the resolution of the 16-bit board at a gain of 10 is 30.5 µV, this represents about 13 counts or a loss of between three and four bits. This means the board in this scenario really is only 12 or 13 bits. Again, this is an oversimplification. These analyses are intended only to illustrate some general principles.
A journey it has been, and it really has only just begun. Hopefully, it has shed some light on some of the pitfalls that can be avoided by not expecting too much from your board. But you are not going to benefit as much from this journey unless you perform these tests on your own board in the environment in which you plan to use it.
The authors thank Ed Loewenstein of National Instruments for reviewing this article and making valuable suggestions.
This article was written by the authors as private individuals and not in conjunction with JPL or the U.S. Air Force.
About the Authors
Ed C. Baroth is the technical manager of the Measurement Technology Center at JPL. He holds a bachelor’s degree in mechanical engineering from City College of New York and master’s and doctorate degrees in mechanical engineering from University of California. (818) 354-8339, e-mail: [email protected].
George Wells graduated from Cal Poly in 1969 with a B.S. degree in electronic engineering. Since then, he has been doing analog and digital design for instrumentation systems in the Instrumentation Section at JPL.
Jet Propulsion Laboratory, California Institute of Technology, 4800 Oak Grove Dr., Pasadena, CA 91109, (818) 354-8339 or by e-mail at [email protected].
Joseph Merrell’s background includes more than 30 years of instrumentation experience with the Air Force Rocket Propulsion Laboratory, in private industry, and currently at the Air Force Research Laboratory. He also has a bachelor’s degree in business and a master’s degree in information systems. Air Force Research Laboratory, Edwards Air Force Base, CA.
Copyright 1998 Nelson Publishing Inc.