For ISDN to continue to grow into more widespread uses, service providers must find ways to reduce its cost. As service providers attempt to penetrate the consumer market, equipment and component manufacturers are experiencing significant cost pressures. Going back even farther in the supply chain, manufacturers of communications semiconductor devices are focusing on reducing test costs to lower selling prices.
One method to substantially reduce costs is multisite test. While multisite or parallel test is not new to the semiconductor test industry, many devices still challenge—and sometimes prohibit—a multisite solution.
The ISDN U-chip exemplifies such multisite test challenges. In particular, the unique activation testing required for the U-chip makes an efficient multisite test difficult to achieve. But with the use of asynchronous test techniques, you can achieve a highly efficient dual-site U-chip test which leads to substantial cost savings.
ISDN U-chip
The U-chip is used in the ISDN Basic Access Interface as shown in Figure 1. From the figure, you can see the U reference point is between the NT1 and the LT blocks in the model.
The U-chip provides the physical interface to the single twisted wire pair connecting the NT1 and LT blocks and resides on both sides of the U reference point. A typical application would have the central telecommunications office as the LT block and the subscriber’s home or office as the NT1 block. The U-chip then would be at each location, driving the twisted pair between them.
The U-chip functionality conforms to the ANSI T1.601 and the ETSI standards. It can drive wire lengths up to 18,000 ft with full duplex transmission of digital information at a rate of 160 kb/s.1
Figure 2 is a simplified block diagram of the U-chip.2 The U-chip receives binary data up to 160 kb/s at the IDL interface input Rx. This data is sent to the framer where it is formatted and scrambled into a 12-ms-long superframe. The DAC converts this data to a four-level 2B1Q (two binary, one quaternary) line code signal to produce an 80-kbaud stream. Then this signal passes through the TX driver that differentially drives an external interface to the twisted pair.
From the U interface, information is coupled through the external line circuitry to the RX receiver and into the ADC. A replica of the transmitted signal generated by the echo cancellation block is subtracted from the converted digital signal.
The conditioned four-level signal is decoded by the data/timing recovery circuitry. This 160-kb/s data stream goes through the deframer where it descrambles the framed data and sends the binary data to the IDL Tx output.
Standard control of the U-chip, such as by a microcontroller, is achieved using the SCP interface. The device also contains crystal-oscillator and PLL circuitry for additional application flexibility.
Testing the U-chip
The test for the U-chip can be grouped into eight major sections:
Continuity.
Leakage.
Digital Functionality.
Transmit Path/Echo Cancellation.
Analog Parametrics.
Pulse Template.
Receive Path.
Activation. These tests, by far, are the most unique and time-consuming.
Activation Tests
The activation tests are a serial sequence of tests intended to measure the capability of the U-chip to be awakened or activated by an incoming data stream. Since the U-chip can be applied to either the LT or NT1 side of the U interface (Figure 1), two separate and unique activation sequences are tested.
Figure 3 shows the test flow for both the LT and NT1 activation tests. Each block in the figure indicates a milestone in the activation sequence. The times shown are the maximum elapsed time allowed between milestones. The total maximum elapsed times are 9 s and 12 s for the entire LT and NT1 sequences, respectively.
The BERT at the end of each sequence checks the bit error rate of the device for at least 1 s and for errors during that time. If the device does not produce the proper bit error rate, both the error check and the activation test will fail. Typically, BERT will take 1.02 s.
Test Time
The issue here is obvious: Theoretically, these combined tests could take 21 s to perform. Although actual times usually are much less than 21 s, these times still are quite long. In fact, the activation tests account for about 67% of the total single-site U-chip test time. Although multisite testing may be a logical answer to a test-time bottleneck such as this, it is not a straightforward implementation.
Single-Sequencer Limitations
The master controller of the activation sequence is the ATE digital pattern sequencer that streams data into the U-chip and checks for its response. For example, when the LT activation sequence starts, the digital sequencer runs digital patterns to set up the device and sends formatted data according to the ANSI activation specification.
This same sequencer then checks for the first milestone by searching for a match on one of the bits from a status register of the U-chip. When the status register says that the first milestone, Frame State 0, has been reached, a test-system timer is strobed, and that elapsed time is tested against the 0.1-s test limit. If the time is within the limit, the digital sequencer checks for the next milestone.
Since each device will behave slightly differently, the times at which each milestone is reached will vary for each device. This variation in elapsed time is what makes multisite testing more difficult.
Figure 4 shows an example of the LT activation elapsed times of two hypothetical devices. As the figure shows, the total elapsed times of both devices are nearly identical, but the points at which each milestone is reached are significantly different.
Ideally, if these two devices were tested simultaneously, you would want the total activation test time to be—at most—that of the longest individual device activation time, or 6.5 s. In reality, if a single sequencer is used, its function requires that it wait until both devices reach each milestone before continuing on with the test. The total time to test both devices will be the sum of the worst-case times of each segment, or 8.0 s.
This method will not work because it causes the test sequence to deviate from the ANSI specification by adding dead time between some of the states. Characterization of exact milestone times also is difficult, if not impossible.
If one device is bad, such that its milestone matches time out, all other sites will fail as well. Consequently, a different method must be used to perform the activation tests for a multisite U-chip test.
Asynchronous Pattern Sequencers
The straightforward solution to this problem is multiple digital-pattern sequencers. With a separate, asynchronous sequencer driving each site, activation tests can be performed as they were in a single-site test. Each sequencer only checks the state of the site that it is servicing. This allows it to move through the activation sequence at the unique pace of that device. While the test program typically will wait for all sites to complete activation testing before continuing, each individual site will have been properly tested according to specifications, returning accurate results that reflect the performance of that site’s U-chip.
Dual-Site Throughput Results
Table 1 shows the throughput improvements achieved with dual-site implementation of the U-chip test. The metric used to measure the multisite benefits is the OE, given by
where: Td = dual-site test time (s)
Ts = single-site test time (s)
For OE, 0% is the ideal target. There is no overhead associated with the multisite test, and the devices are tested completely in parallel.
Throughput improvement, TPI, is defined as
where: TPd = dual-site throughput (units/h)
TPs = single-site throughput (units/h)
The ideal for TPI would be 100%, indicating that the throughput has doubled with the dual-site test.
As shown in Table 1, the 1.2% OE of the activation tests has nearly reached the ideal 0% level. This, again, is due to the highly parallel execution of the activation tests allowed by the asynchronous sequencers.
This low OE is a major contributor to a TPI of 60.8%, since the activation tests are nearly 70% of the single-site test time. Other groups with low OEs include continuity, leakage, and transmit/echo tests, all having a high degree of parallelism during execution.
Conclusion
Asynchronous test techniques allow dual-site production testing of ISDN U-chips. Having asynchronous data-sequencer control dedicated to each test site results in a throughput improvement of 60.8%, accommodating some of the price pressures in the communications market. Asynchronous test techniques also can be used in other applications as well, like those having flash memory and fractional buses.
References
1. ANSI T1.601, “…ISDN Basic Access Interface for Use on Metallic Loops for Application on the Network Side of the NT (Layer 1 Specification).”
2. “MC 145572 ISDN U-Interface Transceiver,” Motorola, 1996.
About the Authors
Daniel T. Hamling is a field product specialist for Teradyne’s A5 and Catalyst Mixed-Signal Test Systems. Before joining the company, Mr. Hamling was a test engineering manager at GEC Plessey Semiconductor and a staff test engineer at Hewlett-Packard. He received a B.S.E.E. degree from the University of Michigan and an M.S.E.E. degree from Stanford University. Teradyne, 4544 S. Lamar, Bldg. 300, Austin, TX 78745, (512) 891-1035, [email protected].
Todd Turner is a product engineering manager in the Narrowband Products Operation for Motorola’s Communications, Transmission, and Access Systems Division. He formerly was a test engineering manager for Final Manufacturing Operations. Mr. Turner has a B.S.E. degree from Baylor University. Motorola, 3501 Ed Bluestein Blvd., Austin, TX, 78721, (512) 934-7897, [email protected].
Sidebar
Glossary of Terms
ADC: Analog-to-Digital Converter
BERT: Bit Error Rate Test
CCSN: Common Channel Signaling Network
CSN: Circuit Switched Network
DAC: Digital-to-Analog Converter
ET: Exchange Termination (Central Office Switch)
IDL: Interchip Digital Link
ISDN: Integrated Services Digital Network
LT: Line Termination (Line Card)
NT1: Network Termination 1 (OSI Layer 1 Only)
NT2: Network Termination 2 (OSI Layers 2 and 3)
OE: Overhead Efficiency
PLL: Phase Locked Loop
PSN: Packet Switched Network
SCP: Serial Control Port
TA: Terminal Adapter
TE1: Terminal Equipment 1 (ISDN Terminal)
TE2: Terminal Equipment 2 (Non-ISDN Terminal)
TPI: Throughput Improvement
U-chip: U-Interface Transceiver Chip
Table 1.
Test Group
OE (%)
Continuity
7.7
Leakage
20.0
Digital
44.1
Transmit/Echo
5.9
Analog
47.3
Pulse Template
105.0
Receive
38.1
Activation
1.2
Total:
14.6
Copyright 1998 Nelson Publishing Inc.
May 1998