The increasing complexity of ICs and boards is challenging today’s conventional board test methodologies. Typically, these methodologies consist of a mixture of functional and in-circuit testing.
Functional testing suffers from high test-program development efforts. More importantly, faults discovered during functional testing are difficult to diagnose. In-circuit testing has the burden of requiring physical access to IC pins or test points. This access is becoming increasingly difficult as board densities continue to rise. In addition, increasing board frequencies are outpacing the capabilities of board testers.
One solution to such problems moves part of the board ATE functionality into the product-under-test. Building on conventional design-for-testability approaches, embedded ATE integrates the high speed and the high-bandwidth portion of external ATE directly into devices to facilitate IC and board-level test, diagnosis, and debug.
At the IC level, embedded ATE technology exists for testing embedded memories, random logic, and mixed-signal functions such as place-lock loops and analog-to-digital converters. Since embedded ATE is within the product, it is reusable.
During board-level testing, IC-level embedded ATE can fully test each device. Other embedded ATE functionality can be added to ICs to provide board-specific test functions.
For example, one board-embedded ATE function is external memory testing. An embedded ATE controller is placed on a device that has access to the board-level memory bus. When activated, the embedded ATE controller takes over the bus and applies a complete at-speed test to all memories on the bus.
This controller also supports various run-time options. It can, for example, be instructed to test only certain memories or apply different test algorithms.
Another existing board-embedded ATE technology handles at-speed interconnect (ASI) testing. It builds upon the standard IEEE 1149.1 boundary scan test approach.
ASI testing uses new at-speed boundary scan cells on each IC as well as an ASI test-controller block to drive necessary timing signals to these new cells. The cells are still scanned directly from the test access port (TAP) using the 1149.1 test clock.
But now the scanned-in test data values can be launched and captured across the interconnect based on high-speed control signals generated by the ASI controllers. This provides the capability to detect and isolate performance-related interconnect problems without interacting with any high-speed tester.
All embedded ATE blocks for both IC and board-level testing can be accessed through the standard IEEE 1149.1 TAP. This access provides a unified way of interfacing the embedded ATE blocks to an external tester. And the external tester only needs to provide data on the five TAP pins at relatively slow speeds (typically under 20 MHz). This feature significantly reduces the tester cost since only a slow-speed, low-pin-count tester is needed, regardless of the operating speed of the board-under-test.
With the complexity of today’s ICs and boards, companies must find an alternative to conventional board test methodologies. Embedded ATE provides a cost-effective solution for addressing these board test issues.
Copyright 1998 Nelson Publishing Inc.
August 1998