For many decades, mixed-signal integrated circuits (ICs) have been tested successfully through conventional testing approaches. But with more and more mixed-signal functions being integrated into complex application-specific IC, companies no longer can afford to rely on conventional methods for testing mixed-signal ICs. Faced with more complex testing challenges, many designers and test engineers are looking for a mixed-signal design-for-test (DFT) solution to help them reap the advantages that their digital counterparts enjoy today.
In the digital world, many years of DFT development are paying off. Digital built-in self-test (BIST) now is economical and, in many cases, the only practical way to get a product to market quickly and cost effectively. As semiconductor technology enables larger gate counts, more mixed-signal functions are being integrated into ICs. These ICs contain hundreds of thousands of logic gates that are designed using a high-level hardware description language such as Verilog or VHDL.
The lack of automation for design and test development for mixed-signal functions contrasts starkly with DFT for digital functions (Figure 1). For this reason, test development for mixed-signal functions has been a major bottleneck in improving time- to-market, decreasing test costs, and increasing test performance. New breakthroughs in mixed-signal BIST, however, provide the opportunity to remove this bottleneck and streamline the test-development process.
Designing mixed-signal ICs for testability can simplify and accelerate design debug and characterization. It can enable more economical testing through the use of lower-cost testers or faster tests. And by providing less intrusive monitoring of performance and better diagnostics, DFT can improve quality, yield, and yield management.
Many issues, however, have prevented the widespread adoption of any single mixed-signal DFT style. New digital BIST solutions are emerging that address these issues.
Mixed-Signal DFT History
Today, the most common approach to mixed-signal DFT is ad hoc. Many companies have developed their own application-specific ways to improve testability, including adding special function modes and instructions, increasing the number of output and input pins, and providing internal loops. These methods exploit the peculiarities of each design and are used because they occupy a small area on the IC and have minimal impact on performance. However, the design- and process-specific nature of these methods makes them very difficult to automate or teach to new engineers.
A notable ad hoc method is loop-around which has been used in telecommunications ICs for many years, both at the IC and board level. The loop-around method exploits the presence of a transmitter or analog-to-digital converter (ADC) together with the complementary receiver or digital-to-analog converter (DAC). The limitations to this approach—gain and noise masking, crosstalk issues, and lack of diagnostic capability—result in a test that is not thorough.
On-chip analog buses are common and were discussed in publications in the mid-1980s. Typically, only an output bus that drives a multiplexed high-performance function output amplifier or a low-performance dedicated amplifier and test pin is implemented. With the latter case, you can see signals while the rest of the IC is functioning normally.
Analog buses are still somewhat ad hoc in nature. The choice of signals to monitor requires understanding the impact of loading on the monitored signals, the diagnostic value of the signals, crosstalk, and the impact of the limited bandwidth of the bus.
Off-chip monitoring of the internal analog signals of an IC almost always impacts its performance. The off-chip version of the signals inevitably has more noise and distortion, leading to a reduction in fault coverage or yield. Nevertheless, the approach has potential for being a methodical test access, especially if it becomes a standard.
The IEEE P1149.4 Standard for a Mixed-Signal Test Bus, which received 93% acceptance on its first ballot in September 1997, uses an input and output analog bus to access analog pins (and optionally, internal nodes) of an IC (Figure 2). The standard primarily is aimed at improving board testability by facilitating measurement of simple passive and active components on the board without a bed-of-nails tester.
Many other analog DFT approaches have been proposed, but most require reconfiguration of the function under test. Some approaches propose that internal operational amplifiers be converted into unity gain amplifiers and cascaded for testing
all amplifiers at once or reconfiguring selected op-amps to provide serial access.
Other approaches suggest connecting the output of a function to its own input via an accurate analog feedback network so that the function becomes an oscillator. Connections to carefully selected internal nodes of op-amps or filters are advocated by other approaches. All these approaches have not been implemented in industry. They require significant changes to handcrafted designs, jeopardize performance, and significantly increase the simulation time, which are not issues in digital design because gate-level design is automated.
The urgent need to reduce the mixed-signal test-development effort that occurs after an IC is manufactured led to virtual test. Virtual test is simulation of the IC being tested, the interface board, and the test program running on the tester. Because simulation times are longer than those for the IC alone, behavioral models for all functions in the IC, interface board, and tester are essential.
This approach can help test engineers better understand the IC and debug the test program, but relies on accurate behavioral models and does not automate test program creation. In other words, virtual test is a test simulation strategy but does not improve testability.
Mixed-Signal BIST
The most promising approach to improving mixed-signal DFT is BIST. In the past, many proposals for mixed-signal BIST have been published, but almost none have been used in industry.
Most of the proposals have the same drawbacks as the various DFT approaches described in this article, including area, impact on performance, and lack of automation. For BIST to supplant conventional mixed-signal test, it must be accurate in the presence of normal parametric variations, noise tolerant to achieve test repeatability, and diagnostic to enable measurement of the key data-sheet parameters that ensure quality and yield.
New mixed-signal BIST solutions must avoid the problems of previous DFT and BIST approaches. The BIST circuits must be digital, synthesizable from Verilog/VHDL RTL descriptions, and suitable for automatic layout. The only connections to the functions being tested must be to the normal inputs and outputs, with no internal analog changes needed. The algorithms must tolerate typical noise and process variations and output key data-sheet parameter values (digitally encoded) and pass/fail bits.
Key mixed-signal functions that need solutions are ADCs and DACs and phase-locked loops (PLLs). LogicVision recently patented a digital method that finds the third-order polynomial that fits the time-domain transfer function of ADCs. The algorithm derives values for offset, gain, and second and third harmonic distortion. The company also has developed other digital techniques to measure the loop gain, lock range, lock time, and jitter of PLLs at full speed, using approximately 1k gates (Figure 3).
The Future of Mixed-Signal Test
When complete BIST for an IC is possible, a tester will only need to provide a few high-speed signals, such as a master clock, a few low-speed test-control signals (five 1149.1 digital pins and two 1149.4 analog pins), and power. The development of a mixed-signal BIST is a significant step in making this scenario possible.
However, BIST will not cause conventional testers to become obsolete. Mixed-signal BIST can enable better use of mainframe testers by facilitating testing of more functions in parallel or more devices in parallel with a small number of high-performance channels allocated to each tested device.
Because each type of mixed-signal function needs a unique test, it is likely that industry will only develop BIST for the most common functions, such as ADCs and DACs, PLLs, and filters. Companies will continue to create ad hoc solutions for other specialized functions, but will benefit from the emergence of the 1149.4 mixed-signal test bus as a standard way to convey continuous variables to and from the functions under test.
A continuum of solutions will be available, ranging from BIST for generic functions to embedded measurement for generic parameters, to parameter translation (which is a form of data compression), and to conventional automatic test pattern generation (ATPG) and conventional test. The most efficient ATPG for mixed-signal testing is for circuits with BIST—the test pattern is digital, simple, and tester independent.
About the Author
Stephen Sunter has worked in the mixed-signal industry for 20 years, 15 of those in IC design, three in test engineering, and the last two years as director of mixed-signal BIST at LogicVision. He was program chair for the International Mixed-Signal Testing Workshop in 1996, co-chair in 1997, and presently is vice-chair of the P1149.4 Mixed-Signal Test Bus Working Group. Mr. Sunter obtained a B.A.Sc. degree from the University of Waterloo in 1978. LogicVision, 101 Metro Dr., San Jose, CA 95110, (888) 584-2478.
Copyright 1998 Nelson Publishing Inc.
September 1998
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