In today’s competitive global marketplace, processor, and personal computer (PC) manufacturers are prompting memory suppliers to provide increased bandwidth in the form of 100-MHz SDRAM, also known as PC100. While products that operate at a full 100-MHz clock will fill the need for increased memory bandwidth, the test requirements of these modules also have the potential to drive up memory costs significantly. Fortunately, the test infrastructure within the industry is evolving dramatically, and new testers are becoming more readily available.
Memory-module prices affect virtually everyone, including PC and other electronics manufacturers, semiconductor manufacturers, third-party memory-module suppliers, memory upgrade providers, service and repair operations, and end-user organizations. With 176 million PC100 modules estimated to be shipped in 1999, test costs can exceed $1.00 per module if the manufacturer uses high-end characterization testers for module production test.1
Most existing testers and handlers fall into two classifications: expensive characterization testers and low-cost production testers, of which many cannot test at 100 MHz. To avoid the large-scale investment of characterization testers, some manufacturers may choose to test PC100 modules at slower speeds. But substandard modules may be produced if you don’t test at full operating speed.
Overcoming the effects of inductance and capacitance at high speed and achieving the necessary measurement precision are among the biggest challenges of testing SDRAM modules at 100 MHz. Measurement precision covers timing, current, voltage, and memory functionality.
The tester architecture must provide a controlled impedance. The most critical part of the design is the pin-driver circuit. A simplified schematic of typical pin drivers for a memory-module tester interfacing to a device-under-test (DUT) signal is shown in Figure 1.
The pin driver can be represented as a pair of switches connecting to Vdd (typically 3 V) and ground, respectively, with series resistances (R1 and R0) placed between the switches and the driver output. The pin driver is connected to the DUT through a 50-W (Zo) controlled impedance path, terminated at the driver with a series resistor (Rs). In cases where the DUT also can drive the signal, such as the bidirectional data pins of memories, a second series termination resistor is placed on the DUT.
The next challenge is to match the timing of all the individual pin drivers to remove the inherent skew from pin driver to pin driver. Due to loading in the test fixture and handler and the DUT, signals of 100 MHz see significant effects, such as reducing the signal level and altering the rise and fall times.
In addition, impedance must be correctly controlled, and the signal lines must be properly terminated to avoid signal reflection. As a result, the tester architecture must be flexible enough to adjust for the wide diversity of parameters for memory-module designs (Figure 2).
To sufficiently weed out defects, the tester must have the flexibility to provide a variety of test functions for each DUT (Figure 3). Each test in the general test flow looks for specific types of failures or defects:
The power test detects module defects that could damage the tester in subsequent tests.
The contact test finds manufacturing defects caused by improper soldering during module manufacturing.
The control-line test assures the proper operation of the control lines in both the active and inactive states.
The address test determines if any of the address lines is open or nonfunctioning.
The data test partially exercises the memory and checks for manufacturing defects, including short circuits, on the data lines.
The algorithmic pattern test performs a specific set of read-and-write operations to assure the memory chips work properly.
The pin-leakage test detects excessive leakage current due to improper soldering or device damage during module manufacturing.
The Vol/Voh test checks the output drivers of the ICs on the memory module.
The Icc test measures the current consumption of the device during specific operations.
When the memory module has a serial presence detect (SPD), SPD test and programming are executed. This should be the final test to avoid programming the SPD when other defects are present.
The choice of the algorithm used to test the memory cell array is important. Some options include the zero-one, checkerboard, walking 1/0, March X, March LR, and galloping patterns. The March X algorithm is the primary testing pattern, although others often are added for more coverage or to guard against difficult-to-detect defects.2
Solutions to Test Problems
Today, OEMs have a number of options for testing 100-MHZ SDRAM modules. New solutions allow these modules to be tested at full operating speed at test costs of approximately 10 cents per module. This is suitable for applications such as high-volume production testing with automated handlers as well as incoming-inspection sampling, failure analysis, and returns processing.
A typical tester designed for affordable testing of 100-MHz SDRAMs integrates a high-speed PC with a user interface and control console for the operator. The tester also includes a dedicated CPU that runs the actual test programs and reports the results back to the PC. Specialized hardware handles address generation and memory reads/writes.
For accuracy of voltage and current, the tester often uses multiple power supplies and parametric measurement units. All communications within the tester take place on a 50-W impedance bus to control loading of signals.
The tester interfaces to the DUT by means of an adapter card or an automated handler. The adapter card contains a connector appropriate for the module design and provides consistent impedance and timing characteristics for coherence with calibration. The automated handler loads modules into a connector in a sequential manner.
Continuing Memory Architecture Changes
The shift to faster SDRAMs is just an indication of future changes in the memory industry, and today’s scenario will repeat itself with other technologies as soon as 1999. As electronics products continue to develop rapidly, the memory industry must continue to evolve to meet the changing needs of users and manufacturers.
Recent announcements from the two largest PC suppliers in the United States, Compaq Computer and Dell Computer, indicate that products introduced in 1999 will incorporate the Direct Rambus memory architecture. In conjunction with Intel’s public adoption of this type of memory, Direct Rambus is likely to become a large factor next year—which, in turn, will bring about new testing challenges.
Other leading memory players are endorsing SLDRAM and Double Data Rate (DDR) DRAM for near-term applications. Compared to older memory types, 100-MHz SDRAM is likely to have a short life span. Recognizing that testing capabilities will remain dynamic, the wise buyer should make sure that new 100-MHz SDRAM testers can upgrade to handle future technologies.
1. Custom research by Semico Research, Phoenix, AZ.
2. van de Goor, A.J., Testing Semiconductor Memories: Theory and Practice, Wiley, 1996, p. 112.
About the Author
Joseph C. Klein, Ph.D., vice president of engineering, joined Tanisys Technology in November, 1997. He has more than 15 years of experience in electronics as vice president of engineering/research and development for PNY Technologies and as worldwide manager of semiconductor memory products at IBM PC. Dr. Klein received a Ph.D. from the University of Pittsburgh, Graduate School of Chemistry. Tanisys Technology, 12201 Technology Blvd., Suite 125, Austin, TX 78727, (512) 257-5395, e-mail: [email protected].
Copyright 1998 Nelson Publishing Inc.