EE-Evaluation Engineering interviewed six industry leaders as we compiled our report on the state of two very separate forms of ATE—IC and board. IC ATE companies were concerned about the downturn in their businesses, but they also saw 1998 as a time to complete development of the products that will be needed for D-RDRAM and system-on-a-chip (SOC) next year. Board ATE companies are progressing on a more evolutionary path, anticipating further loss of physical test access and formulating test plans accordingly.
IC ATE: A Strategic Inflection Point
Or Just Extreme Cyclicality?
Worldwide economic uncertainty, falling prices for PCs, and the current semiconductor fab overcapacity form the setting for this article. As Bill Bottoms, chairman and CEO of Credence, put it, “The current business cycle is exhibiting itself more aggressively than ever before in the history of the industry. We have never seen a more rapid decline in business volume in the IC ATE industry.”
Against this backdrop, many technological and economic factors are converging:
Demand for SOC—large-scale, system-solution chips, generally with analog, logic, and memory functions.
Development of faster devices with high pin-count.
The need to test devices such as D-RDRAMs at full speed.
Migration to chip scale packaging (CSP).
The need for lower-cost testing that implies shorter test preparation and actual test times.
Outsourcing of IC manufacture and test.
By the end of 1999, IC ATE manufacturers will know whether the relative emphasis they placed upon these items today was justified. It’s not certain if or when the communications industry-driven growth in SOC may overshadow the high-end PC-driven need for faster logic and memory devices.
Nor is it clear how soon high pin-count ICs and the increased use of CSPs will force the replacement of older, slower, smaller testers. There also may be further global economic surprises that will exacerbate the present slowdown in the semiconductor manufacturing industry.
Nevertheless, IC ATE companies are confidently developing the products they think will be required to test next-generation ICs, even if they can’t accurately plan the timing of that demand.
For many years, the introduction of each technology has forced semiconductor manufacturers to purchase new testers. This often-repeated scenario has resulted in an IC ATE market driven by capacity expansion as well as the need to replace obsolete equipment. Today’s problem is to determine the degree to which new technologies will require completely new kinds of testers, not just faster, bigger models of existing types.
Credence’s Mr. Bottoms believes that SOC may represent a technological inflection point—a fundamental change to the nature of both the semiconductor manufacturing and ATE businesses.1 “Older platforms will not be able to test these new devices. That will drive a demand for the capability to test a device type that the installed base can’t do.”
Neil Kelly, chief technologist at LTX, agrees. “Most semiconductor manufacturers have announced their intention to move toward SOC. Either they are lining up their own intellectual property (IP) to enable them to make these devices or they’re forming alliances with other companies where there are holes in their IP portfolio. In my opinion, the trend to invest only in test equipment that can be upgraded or that can address SOC today has caused a stall in capital equipment investment.”
“The industry is going through a rapid product obsolescence stage. It requires the replacement of the installed base technology in all areas simultaneously, specifically in the memory area,” said Tom Newman, vice president of corporate relations for Teradyne. “There is a major transition coming in technology related to Rambus® and SLDRAM which will require 800-MHz testers and beyond.”
Also emphasizing speed and “the need to become a one-stop shopping service” was Nicholas Konidaris, the president, CEO, and chairman of Advantest America. Customers require a complete solution in the form of ATE plus handlers plus interface. We offer 1,024-pin, uncompromised, 1-GHz test capability in logic and Rambus® or fast SRAM memory test systems.”
Today’s Opportunities
Testers that are selling today address the following areas:
Higher yields from 200-mm wafers.
SOC and mixed-signal chips.
Wide bus/high pin-count devices or parallel device testing.
In the present economic environment, delays are being experienced in front-end expansion (fab construction) and the change from 200-mm to 300-mm wafer processing. “People see that as a very painful and expensive step they would like to put off as long as possible,” said Mr. Newman of Teradyne. “By shrinking line widths from 0.35 to 0.25 m m or from 0.25 to 0.18 m m, they get a lot more dice per wafer, and they need a lot more testers. One of our customers was getting about 200 dice per wafer and now gets more than 1,000 from the same 200-mm wafer.”
There is growth in the part of the market that needs to have full SOC test capability. Telecomm applications continue to drive this area, with requirements for sophisticated analog-to-digital converter, digital signal processing, and RF test capabilities on the same chip.
Commenting on the latest SIA National Technology roadmap report, Mr. Kelly of LTX said, “I interpret it to mean that the process capability for SOC actually is in place and that the investment in the future will be made in the design and test areas rather than in the process area. People don’t really need faster Pentiums and much deeper memories right now. What they need are SOC devices.”
Also, some new testers are being bought to test higher pin-count devices or to achieve economies of scale by testing many smaller devices in parallel. High-speed digital designs are using very wide buses to avoid the expense of stripline PCB traces which would be required otherwise to handle off-chip data rates over 100 to 200 MHz. Wide buses mean more device I/O pins.
“If you really have to test a device that has 790 pins, you can’t test it on a 512-pin tester,” said Mr. Bottoms of Credence. “As the pin-count increases, we will have a drive for capability where there is no capacity to test at that level even though people may have older machines that are not being used.”
In spite of these isolated areas of market activity and the fact that the number of IC units tested will be higher this year than in 1997, the overall level of business is down significantly. The decline was described by Mr. Konidaris of Advantest as, “… a unique event that happens every 30 years.”
“I don’t think this is a normal cyclical downturn,” added LTX’s Mr. Kelly. “I think it’s much more significant than that.”
Tester Niches
Teradyne’s Mr. Newman described additional capabilities in IC testers. “If you are in the mixed-signal world, you not only need 6-GHz analog capability, but also 400- MHz digital capability on lots of pins. All of Teradyne’s high-end logic testers are being ordered with embedded memory test capabilities as well as with some sort of analog test capability.”
Technology is moving so fast that only a general-purpose solution will address a manufacturer’s uncertain product mix, according to Mr. Kelly of LTX. “Our SOC tester, called FUSION, really is a superset of everything that’s required to test all the other devices as well. A semiconductor manufacturer making SOC as well as mixed-signal devices and processors and general logic ICs can test all those devices on a single platform.”
Advantest is concentrating on 1-GHz logic and memory testers. Mr. Konidaris said that only dedicated testers can provide the highest levels of performance. “Each class of device has its own problems, and unless you optomize the system to address those problems, you cannot offer the required performance, or cost, or both. We also believe that mixed-signal testing will be accomplished with digital testers and digital techniques. Our strategy is to provide mixed-signal capability through those systems by offering additional options,” he explained.
Replacement of older, product-specific testers by the new SOC testers may continue until all the capabilities match those of high-end niche testers—over 1,024 pins, at least 1-GHz speed, and RF measurements. But, it may not be economical to do this.”
It is tempting to think that you can offer a vanilla system that can do everything. But it is not practical today,” said Mr. Konidaris.
In the meantime, very fast devices will require very fast testers. SOC testers will provide high-performance analog, logic, and memory test, but not the very highest speeds of the dedicated testers.
Test Technology
IC testers and semiconductor technology have a symbiotic relationship. Integration of complete test-instrument suites and pin drivers has made very compact test head assemblies possible, although liquid cooling is required to remove heat from the dense circuitry. “Today, we have a tester that has 768 pins, and it only requires 4 kW of power. Previously, 768-pin testers needed tens of kilowatts,” said Credence’s Mr. Bottoms. “We use stabilized CMOS circuitry so that we can get high timing precision.”
“Because of the different speeds and drive requirements of different parts of the tester, we use bipolar, CMOS, and GaAs technologies, ” explained Mr. Kelly of LTX. “Four chips contain most of the electronics to implement two tester channels.”
High levels of circuit integration reduce test head size and floor-space requirements and accommodate increased numbers of test pins and more comprehensive levels of testing per pin. Smaller geometry test heads reduce round-trip delays, an important consideration when interfacing a tester to a wafer prober. In addition to higher speeds, higher timing measurement accuracy also is needed because many devices incorporate and interface to fast buses.
Related Test Issues
Just as he highlighted reusable IP as being the key to SOC design capability, Mr. Kelly said, “With LTX’s Test IP, you can reuse a test method from one program to the next. Test methods are represented by an icon, and they can be linked to a new test program simply by drawing lines between them.”
Mr. Newman discussed Teradyne’s test-development tools. “We’ve introduced VX software to help customers in the mixed-signal world translate from design to test data bases. We have software simulators for all of our machines to help develop and debug test programs.” This approach facilitates significant test program debug before first silicon even arrives.
BIST has a place in the overall test scheme, depending upon the particular application. Mr. Bottoms of Credence expressed it this way: “Semiconductor manufacturers build transistors a billion at a time. The economics won’t be met if we test them one at a time. BIST and other design-for-test (DFT) technologies are not competing with traditional ATE hardware. They are supplementing it.”
“At some point, maybe BIST will allow you to reduce test costs, but I think that is a long way from where we are now,” said Mr. Newman of Teradyne. “BIST is one of the areas of DFT experimentation. I don’t think the industry has settled on an approach yet.”
Built-Off Self-Test (BOST) is Credence’s answer to long round-trip delays in older testers. “By putting a custom BIST chip immediately adjacent to the DUT, you can overcome limitations of round-trip delay and tester pin-count. Because the BIST test is used in parallel with other tests, the tester throughput goes up,” explained Mr. Bottoms.
Summary
The manufacturing processes themselves are changing, the chip and interconnect materials are changing, and so is the shape of the business model. One report sees the industry of the future comprising SOC manufacturers linked to their IP partners, producing very large scale designs of interconnected, reusable IP blocks. Other companies would supply the lower-cost, high-volume parts to help defray fab expenses.2
While the IC ATE industry pursues today’s meager sales opportunities, the industry’s leaders are working hard to understand how the many converging forces shaping their businesses will interact and when. New technologies are being developed on several planes simultaneously: SOC may be the most comprehensive because of its variety, but D-RDRAM and SLDRAM speeds and the very large mixed- signal logic chips with embedded memory remain challenging.
There is general agreement on the long list of factors that will influence the future of IC ATE. However, no one is certain about the precedence of the factors relative to each other nor of the timing of the hoped-for market upturn.
References
1. Grove, A.S., Only the Paranoid Survive, Currency Doubleday, 1996.
2. Boyd-Merritt, R., “The IC Hits Midlife Crisis,” Electronic Engineering Times, Sept. 30, 1998, pp. 15, 16, 138.
Board Test Methods Combine to Address Loss of Access
The continuing reduction of physical test access is a major trend driving the board ATE business through 1998 and beyond. Certainly, there are other factors such as time to market, cost of test, outsourcing of manufacturing, built-in self test (BIST), and the increasing use of ball grid array (BGA) packaging and chip scale packaging (CSP). But, because physical access is a fundamental concept upon which test fixturing and in-circuit test have been based, lack of access is redefining the test process.
Hewlett-Packard recommends that customers use a blend of test technologies rather than trying to achieve high fault coverage with just one approach. “Optical inspection does a good job of dealing with very small components and also can identify missing, tombstoned, or rotated parts,” explained Kamran Firooz, general manager of Hewlett-Packard’s Manufacturing Test Division. “For BGAs, CSPs, and devices under shields, X-ray is the only technology that can determine the quality of hidden joints. Electrical test using boundary scan and vectorless techniques also helps overcome limited access for both analog and digital components.”
Michael Schraeder, president of GenRad’s Electronic Manufacturing Systems division, added, “Many of our customers are trying to move functionality earlier in the manufacturing process. They want to make sure that they won’t be running into any basic functional faults that could take a lot of time later in the process.
“For example, PC motherboard manufacturers are verifying PCI bus operation before going to a full board-level functional test. This allows the PCI bus to be used for electrical access even though physical access has been reduced,” he continued.
HP has developed analog boundary scan techniques specifically to address boards with limited test access. Components between selected nodes are treated as clusters, and faulty components within clusters can be identified unambiguously by special test programs.
GenRad’s, experience with mixed analog and digital telecomm and automotive systems has prompted the company to provide additional analog functional test capability. The analog and digital subsystems are synchronized to work in parallel.
Y2k
Concern over the Y2k effect may be a key contributor to board ATE growth in 1999, according to Mr. Schraeder. Some people think that replacing old equipment may be a good way to improve test capability, at the same time ensuring Y2k compatibility. “There are many systems in the field that need to be upgraded for the year 2000. But in many cases, customers want to make sure they won’t have any problems as they move forward, especially if they already have specific information systems in place,” he said.
HP’s Kamran Firooz agreed: “We are in the process of determining how best to support older equipment. Where software and hardware changes can be made easily, we are upgrading equipment in the field. And, as for new equipment, all new products coming off the line since last July are Y2k compliant.”
The Future of Board Test
In the future, GenRad’s Mr. Schraeder expects to provide customers more and better information. “We are focused on collecting data in manufacturing and providing that information in a timely fashion in the most usable form. Test personnel want to get information about unexpected failures or downstream problems so that they can be caught earlier in the process,” he said. “You learn a lot from the experience of releasing a program or new board to manufacturing, and you want to ensure that the same mistakes aren’t made again.”
Software also is key to HP’s vision of the future for board test. Mr. Firooz presented a view of the test process that started with board CAD data.
“Imagine you have a program that can generate the test programs for X-ray, vision, and electrical test systems starting from CAD data. Suppose that the program generators are linked so that later test systems won’t repeat those tests performed by previous systems. We can get the automatic testing equipment to be aware of other systems and eliminate redundant tests while filling in any gaps between systems,” he explained.
Another aspect of test software is reusability. “Today, generation of high-fault- coverage test programs costs time and people because it is more of a manual operation,” said Mr. Schraeder of GenRad. “The focus for the future is to provide a test library and templates, so when certain functionality is required, they can be plugged in.”
BIST is appearing in many forms. “It is getting some recognition, but not as much as you would expect,” said HP’s Mr. Firooz. “It may take an extra few weeks to design BIST in the board. Some customers are not willing to make that investment, so they ask the manufacturers to do the best they can without using BIST. Also, for very cost-sensitive markets, it does add cost.
“But probably a bigger factor is designers’ poor knowledge of BIST. The companies that prepare their design team for BIST can obviously succeed,” he concluded.
“Over the last 18 months, where customers are losing access, they’ve been trying to add BIST,” said Mr. Schraeder. It’s still in a manual form. But BIST, including boundary scan, is definitely something that many customers are starting to do,”
And what about system-on-a-chip? “That’s where you need tools like boundary scan, BIST, and ways to access the card to verify the functionality of that device on the board,” said Mr. Schraeder.
Copyright 1998 Nelson Publishing Inc.
December 1998