Just about every design engineer must face the challenges of integrating an increasing number of circuit functions in a continually decreasing board space. With only limited space available, conventional miniaturization techniques rapidly approach a critical mass from a testing point of view. This article demonstrates how a successful test strategy can be implemented for a PCMCIA (PC Card) module that uses chip-on-board (COB) technology in conjunction with boundary scan test.
Product Definition
The product to be tested is a complex control unit that communicates with industrial controls in service applications. Due to the required mobility and performance, a Type II PC Card and a laptop computer as host is the preferred solution. Existing standardization limits the usable PCB space to approximately 45 mm × 65 mm with a maximum mounting height of 3.5 mm including the board.1
A rough estimation showed that conventional surface-mount technologies would need two or three times the space, even if a field programmable gate array (FPGA)-based design were used. Due to the relatively small quantities (less than 1,000 PC Cards per year), the use of application specific integrated circuits (ASICs) is not profitable. The necessary integration of two separate memory blocks presents another problem.
COB Solution
Based on a thorough evaluation, a COB-based solution for both the FPGA as the central device and the memory devices is the optimal strategy for this project. These devices are glued to one side of the board as dies and then bonded. Conventional single outline pack (SOP) components are assembled on the other side. This results in a total height of approximately 3 mm.
An advantage of the FPGA is the standard implantation of the boundary scan structure compliant to IEEE 1149.1.2 Boundary scan also is the preferred general test strategy for production because it permits unrestricted test access even after die passivation.
Boundary Scan Test Strategy
In this application, the buffer IC and FPGA are in one scan chain. Because the FPGA is the core of the PC Card’s functionality, it provides access to nearly all circuit components (Figure 1).
Based on the defined test partitions, an arithmetical fault coverage of about 90% on the signal pin level is achieved (Table 1). The same fault models (stuck-at 0/1, opens, shorts, bus faults) are used for both COB networks and soldered connections.
Some pins cannot be tested because they are disconnected or set to a stable potential via resistors. In the latter case, they are statistically contained in the power/ground (PWR/GND) nets not testable.
Another reason for limited fault coverage becomes obvious when testing the logic cluster. Here the highly sequential and closed character of the circuit allows only minimal static testability via boundary scan. This typically is accompanied by a vague pin class diagnosis in case of errors (listing of several pins as potential error sources). Essentially, the same diagnosis occurs when testing the infrastructure.
Peripheral networks are included in the connection test via external test modules. Altogether, the UUT’s scan-chain length is 872 scan cells.
The serial FLASH, on one hand, enables the FPGA to adapt the PC Card to various transfer protocols. On the other hand, it contains more card-specific information that can be read if needed. The variable firmware can be programmed into the FLASH via boundary scan as well.
Practical Implementation of the Test Strategy
A test system from GOEPEL electronics is used to test and program the PC Card. The SCANTURY® 2050 PC-Based Boundary Scan Tester runs under Windows NT. The CASCON-GALAXY® system software provides an integrated development environment for test and programming procedures (Figure 2).
The test strategy reflects the existing test partitions in separate test steps. In an additional step, the serial FLASH is loaded after die passivation.
Both peripheral and embedded boundary scan nets are checked during the interconnection test. A standard TCK frequency of 7 MHz is used. For reasons of time, only the FLASH is programmed at 20 MHz on TAP1. TAP2 is inactive during this procedure. As a result, the entire test and programming sequence takes only 15 s.
Summary and Prospects
The target of the project—to gain a substantial reduction in circuit size by using COB—is fully achieved. Additionally, boundary scan provides an efficient and cost-effective test strategy. The advantage of programming the FLASH device also improves efficiency.
New packaging technologies such as µBGA or Chip Scale Packaging (CSP) open new opportunities for further miniaturization. Coupled with boundary scan, the challenge of minimizing test issues can be met successfully.
References
1. PCMCIA/JEIDA, PC Card Standard, 1997.
2. IEEE 1149.1-1990, Standard Test Access Port and Boundary Scan Architecture.
About the Authors
Dr.-Ing. Hans-Joachim Freitag is the manager of CiS Institute for Micro Sensor Technique GmbH in Erfurt. During his career, he has worked with Carl Zeiss Jena and managed the Numeric Measurement Systems team. He also earned a doctorate at Technical University Dresden.
Heiko Ehrenberg studied electronic information and measurement technology at the University of Applied Sciences in Mittweida. He has worked with GOEPEL electronics as an application engineer since 1996. He now is manager of the company’s North American Technical Support Center in Austin, TX.
Huntron, 15720 Mill Creek Blvd., Mill Creek, WA 98012, (800) 428-9265, www.huntron.com.
Table 1.
Test Partition
Circuit Pins
Boundary Scan Testable Pins
Fault Coverage
Remarks
Infrastructure Nets
16
16
100%
Pin Class Diagnosis
Embedded Boundary Scan Nets
80
80
100%
Peripheral Boundary Scan Nets
140
140
100%
With External Test Modules
Logic Cluster
105
32
14%
Pin Class Diagnosis
RAM Memory Cluster
502
494
98%
FLASH Memory
8
4
50%
Nets
220
—
0%
Implicit Test Only
Total Signal Pins
851
766
90%
Without Nets
Total Board Pins
1,071
766
71%
Copyright 1999 Nelson Publishing Inc.
August 1999
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