Jitter Testing in Production

As the operating frequency of ICs increases, the jitter in the clock and the I/O signals becomes a larger percentage of the available timing margins. This reduces yield or even causes device failures, serious production problems, and possible delays in product introduction.

While jitter analysis is becoming increasingly critical in semiconductor ATE, engineers find that current digital testers cannot measure the jitter, and analog or mixed-signal testers lack the digital speed and performance to do so. To compound the problem, none of the testers today can properly measure the jitter of phase-locked loops (PLLs) that have low-frequency modulation at their output or modulated reference signals at their input, both designed to spread the spectrum and reduce EMI.

A time measurement unit (TMU) can make these jitter measurements in a few milliseconds with a resolution to 1 ps for signals up to 800 MHz. It can provide multiple channels that are either single-ended or differential. Each pair of channels can form a complete time interval analyzer (TIA). The advantage of multiple channels is in the simplification of load-board designs with the corresponding reliability improvement.

Frequency synthesizers, also called clock generators, are increasingly popular as systems become more complex and begin to use multiple clocks. They use PLLs to generate different frequencies, replace various crystal oscillators to save board space and cost, and keep the high-frequency clock generator in a confined area.1

If a source has excessive high-frequency jitter, a PLL with low loop bandwidth can act as a low-pass filter. PLLs also allow clock-skew control, and a clocking PLL modified using spread-spectrum techniques can alleviate the effects of EMI. An in-depth understanding of the complex time and frequency measurements of these PLL-based systems is critical as clock speeds continue to accelerate.

Few high-speed synchronous systems are exempt from clock jitter effects (see sidebar). Many common parts require jitter testing in production:

Digital parts, such as CPUs and memory controllers, with embedded PLLs for multiplying the clock.

Graphics controllers with embedded PLLs for the pixel clock. Jitter in the clock causes image degradation.

Datacom devices, such as local area network (LAN) and low-voltage differential signaling (LVDS) interfaces.

Telecom devices, such as those used in a synchronous optical network (SONET) or an asynchronous transfer mode (ATM) network, and frequency synthesizers.

High-speed serial devices used in FibreChannel and Giga-Bit Ethernet, with signaling requirements that put strict limits on jitter.

Measuring Jitter in PLL-Based Clock Systems

Since the causes of PLL jitter are analog in nature, they tend to go undetected in many digital designs. The most common source for jitter is power supply noise, which is asynchronous and difficult to measure. To accurately tackle the task of cycle-to-cycle jitter measurements, TIAs are necessary.

The output of the clock is connected to a TIA to measure the difference of time periods of consecutive clock cycles. The maximum of this difference over multiple cycles is the cycle-to-cycle jitter.1,2 In general, a TIA has the following advantages:

High measurement rate (2×106 time measurements/s), each with a 1-ps single-shot resolution.

Coherent measurements because they are derived from a continuously running clock. This allows the instrument to compute the short-term jitter, long-term jitter, and average frequency from the same set of measurements acquired in a single block.

All pulses of the input signal are counted, providing complete temporal information on the signal.

A Faster system-based architecture.

In addition to measuring jitter, a TIA provides comprehensive characterization of a PLL. It measures frequency stability, step response, loop-filter bandwidth, start-up time, and frequency settling time. For PLLs that use the spread-spectrum technique, a high-speed TIA directly measures the modulation waveform and the attenuation of the loop filter for modulation and jitter at the input, even if this modulation is asynchronous to the clock frequency (Figure 1).

The loop-filter bandwidth is important in PCs that use modulated clock sources. A filter with the wrong response may work correctly with unmodulated inputs but not with modulated inputs. With a TIA, the response of the loop filter is measured quickly by applying a frequency or phase step at its reference input. This produces a voltage step at the input of the loop filter in the PLL.

Since the output of the loop filter controls the frequency of the output oscillator, the change in the PLL’s frequency over time represents the loop filter’s response to a step function. The bandwidth of the loop filter can be determined from this step response. Phase or frequency steps can be easily produced by digital testers, eliminating the need for special signal sources.

Signal-Integrity Measurements

As operating frequencies go up, the wave shape of the signal becomes a critical factor. The rise and fall times of the signal are major parts of the timing budget. For frequencies above 200 MHz, these waveform-integrity measurements can enhance a digital test to allow tighter timing margins than can be achieved with the standard high/low comparator testing. In other words, at high frequencies, the signal no longer can be viewed as ones and zeroes, and the analog characteristics must be taken into account.

A TIA can make these measurements at high speed before running the digital vectors for functional testing. This also allows the use of digital testers that are slower than the device, eliminating the need to upgrade the tester speed.


LAN devices typically have many digital pins and only a few analog pins. The analog signals must be tested for jitter, rise and fall times, and other timing parameters. These signals have special wave shapes that are difficult for the typical digital tester to handle.

Advanced TMUs can make these measurements in parallel, which speeds up the test process. When integrated into digital or mixed-signal testers, they can extend the capabilities of the tester at a low incremental cost. The enhanced signal-integrity measurements can improve reliability and yield.

Graphics and multimedia chips present a situation similar to the LAN devices. There are only a few analog pins—the RGB outputs—which usually are from 8-bit digital-to-analog converters, and the PLL clocks that are used to step up the reference frequency from the motherboard. In graphic devices, these PLLs are running at frequencies greater than 300 MHz.

Jitter in the PLL causes image degradation or even total device failure. A TIA that has waveform capture capability can be used for production testing of PLLs and verifying the quality of the RGB outputs, enabling the use of a digital tester for the remaining tests.


Jitter and waveform integrity measurements are becoming a necessity in production testing due to increasing I/O frequencies and the use of embedded PLLs. New instruments, which are suitable for production testing, can be used to address this problem. These instruments must be accurate enough to meet current device requirements and fast enough to provide economic solutions in semiconductor ATE. Their integration into today’s testers can extend the useful life of current testers.


1. “Clock Terminology,” Application Note, Cypress Semiconductor Corp., October 1994, Revised July 9, 1997, http://www.cypress.com/pub/appnotes/clocterm.pdf.

2. “Jitter in PLL-Based Systems: Causes, Effects, and Solutions,” Application Note, Cypress Semiconductor Corp., May 1995, Revised July 7, 1997, http://www.cypress.com/pub/appnotes/jitrpll.pdf.

About the Authors

Shalom Kattan founded GuideTech in 1988. Prior to that, he worked on the timing calibration system of a linear tester at Attain and spent four years at Hewlett-Packard in the time and frequency division. Mr. Kattan holds an M.S. in software engineering and a B.S. in electrical engineering from the University of Florida. GuideTech, 470C Lakeside Dr., Sunnyside, CA 94086, (408) 733-6555, [email protected].

Dave Harris joined Credence Systems in 1995. He previously worked at National Semiconductor, Teradyne, and Attain. Mr. Harris also spent eight years in IC design at Ratheon Semiconductor and Precision Monolithics. He earned a B.S. in electrical engineering from Arizona State University. Credence Systems, 215 Fourier Ave., Fremont, CA 94539, (510) 623-4793, [email protected].


What is Jitter?

Clock jitter is defined as the deviations in a clock’s output transitions from their ideal. The deviation can either lead or lag the ideal position. Jitter can be expressed in units of time, a percentage of frequency, or absolute value.

There are three main categories of jitter measurements: cycle-to-cycle, period, and long-term. Alternatively, both cycle-to-cycle and period can be collectively referred to as short-term jitter. Cycle-to-cycle jitter is the change in a clock’s output transition from its corresponding position in the previous cycle. Period jitter is a measure of the variation in the length of single periods of the signal. Long-term jitter is a measure of the maximum change in a clock’s output transition from its ideal position over many cycles due to random phase shifts or oscillator frequency instability.

There are four primary causes of jitter. Power supply noise is the largest, although not always a constant, contributor to jitter. Changes in the input phase of an embedded PLL, random thermal noise from the crystal reference or any other resonating device, and random mechanical noise from vibrations of the crystal reference also contribute.

LAN specifications break down jitter into periodic

, deterministic, and random jitter.

The capability to separate these components is becoming increasingly important in the test of LAN devices.

Copyright 1999 Nelson Publishing Inc.

September 1999

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