EMC Design Practices: Preserving Signal Integrity Part 5

EMC has two parts. The first, intersystems EMC, addresses a system’s capability to operate within its external environment and determines its compliance with governmental EMC requirements. Intersystems EMC includes both design compatibility (radiated and conducted emissions and susceptibility) and operational compatibility (frequency, amplitude, separation, and time management).

The second, intrasystems EMC, addresses the internal RF/signaling characteristics that affect a system’s functional operation, performance, and reliability. Sometimes this is described under the heading of self-compatibility. The internal RF sources that create most intrasystems EMC problems also create the intersystems emissions problems.

The principal effect of intrasystems EMC problems in high-speed digital systems is signal-timing variation caused by waveform distortion, crosstalk, non-monotonic signaling, device I/O capacitance differences, ground bounce, and simultaneous switching noise. Digital-systems designers lump these primarily analog intrasystems EMC problems together under signal integrity. Understanding the basics of signal integrity will help designers minimize changes occurring late in the design cycle that can degrade operational performance.

Just being aware that signal timing may be adversely affected by indiscriminately adding EMC suppression components is a big step. This article does not cover all aspects of signal integrity, only the principal ones affected by adding suppression components to an otherwise fully functional system.

Recognizing Timing Problems

The most important elements of signal integrity are timing, timing, and timing. Intended signals need to reach their destination at the same time all the time. If an unintended signal, such as internally or externally coupled noise, reaches the destination first, changes the signal rise time, or causes it to become non-monotonic, it’s a timing problem. If added suppression components distort the waveform, change the signal rise time, or increase delay, it’s still a timing problem.

It’s easy to visualize that circuit design, parts placement, and trace routing affect timing. It’s not so easy to visualize that timing also is affected by trace-width variations, PCB dielectric, receiver input sensitivity, transmission-line termination, fan-out, crosstalk, electric field/magnetic field (EF/HF) radiation, and suppression component selection. And with today’s high-speed circuits, timing is critical.

How Much Timing Variation Can Be Tolerated

A 500-MHz clock requires a bandwidth of 5 GHz and completes one cycle in 2 ns—or very fast. The fundamental determines the pulse width. The rise time establishes the pulse bandwidth and is a function of the number of harmonics.

In general, nine harmonics are required to establish the rise time. This relationship is illustrated in Figure 1. Because there is little change in rise time as we add harmonics, the amplitudes of the higher-frequency harmonics should be reduced.

A 500-MHz clock pulse can be approximated by a 50% duty-cycle trapezoidal waveform of 1,000-ps duration with a worst-case rise time of Tr = 500 ps, or more typically a rise time of approximately Tr = 250 ps. Because the clock edge rate is used to synchronize a system’s numerous logic circuits, threshold crossing time, clock jitter, and clock/signal arrival time (skew) are very important.

Delay is analogous to reducing the clock speed and must be minimized. Skew should be 10% or less of the clock cycle time. For a 500-MHz clock, this means under 200 ps.

Signal Propagation Time in a Dielectric

In a vacuum, signals travel with a velocity of Vv = C = 3×108 m/s. Within PCBs, however, the velocity is reduced by the dielectric. The velocity in a dielectric is Vd = C/(Î r) 0.5 m/s.

Trace propagation time is the inverse of the velocity calculated as Tpd = (Î r) 0.5/C s/m. This equates to Tpd = (LC)0.5. This last expression is very important. It indicates that any series, parallel inductive, or capacitive suppression components applied to PCB traces or logic devices will increase delay.

On high-speed PCBs, signals are distributed using either microstrip (signal trace located on the PCB surface above its return plane) or stripline (signal trace located between two return planes). For FR-4 material with (Î r) = 4.7, the stripline propagation time is Tpd = (4.7)0.5/3×108 = 7,220 ps/m or 180 ps/in. This is approximate because (Î r) varies locally within a PCB and from one PCB to another.

High-Speed Signal Traces as Transmission Lines

Continuing with the 500-MHz example, the fundamental wavelength in FR-4 material is 11.07 in. (wavelength = C/[frequency × (Î r)0.5]). For a CW signal, the concern would be standing waves as the trace dimension reached ¼ wavelength.

For a pulse, the concern is the critical line length (CLL) determined by the rise time or CLL = Tr /(2.5 × Tpd). For a rise time of Tr = 250 ps and a propagation delay/unit length of Tpd = 180 ps/in., the CLL = 0.5 in. This is the length where transmission-line effects become significant and the line must be terminated in its characteristic impedance. Doing this creates a flat transmission line with maximum power transfer and no troublesome reflections.

Under matched conditions, increasing the transmission-line length only affects the delay and attenuates the signal amplitude; it does not significantly change the waveform. In general, only one end must be terminated to reduce waveform distortion, but the timing for intermediate points will depend on which end is terminated. With load termination, the incident signal is matched. With source termination, the signal is matched when its reflection returns to the source.

Proper Transmission-Line Termination

Incorrect termination impedance can result in ringing (oscillatory behavior from excess inductance) or signal rolloff (attenuation of higher frequencies from excess shunt capacitance) and prevent driver outputs from reaching associated receiver switching levels. Ringing can cause non-monotonic behavior; for example, the signal crosses the switching threshold several times.

Depending on phase relationships, crosstalk and external EF/HF field coupling also can cause non-monotonic behavior and change signal timing. Figure 2 illustrates how this occurs.

The non-monotonic behavior of clock lines is critical because of multiple clocking. This is not quite as big a problem with data lines. Other side effects of ringing are increased EF radiation and line-to-line crosstalk. On the other hand, rolloff increases the rise time and associated delay of the line. This generally reduces EF radiation at the higher frequencies and line-to-line crosstalk. It also increases signal delay and reduces system throughput.

Signal Delays

Both microstrip and stripline inductance and capacitance principally are related to the length and width of the trace. For a 10-mil stripline centered between two planes 20 mils apart, the capacitance is approximately 50 pF/ft or 4.166 pF/in. Since Tpd = (LC)0.5 = 180 ps/in., L = 7.78 nH/in. The input capacitance variation for CMOS devices typically ranges from 2 pF to 7 pF.

Not much, but consider what happens to the delay. For a 1-in. line with no additional capacitance, the delay is 180 ps. For the same 1-in. line terminated with a 2-pF part,

Tpd = (7.78 × 10-9 × 6.166 × 10-12)0.5 = 219 ps

With a 7-pF part,

Tpd = (7.78 × 10-9 × 11.166 × 10-12)0.5 = 295 ps

There is a 76-ps variation in timing between parts, with a 115-ps additional delay resulting from the 7-pF capacitance.

For a 10-in. line with no additional capacitance, the delay is 1,800 ps. The same line terminated with a 2-pF part,

Tpd = (77.8 × 10-9 × 43.66 × 10-12)0.5 = 1,843 ps

With a 7-pF part,

Tpd = (77.8 × 10-9 × 48.66 × 10-12)0.5 = 1,946 ps

Now there is a 103-ps variation in timing between the same parts. Also, there is a 146-ps delay resulting from the 7-pF capacitance, an increase of 31 ps. The longer the trace, the worse the problem.

With Monte Carlo analysis, the timing differences from component variations can be resolved, not easily—but it can be done—and the system’s timing adjusted accordingly. Remember, the effects of fan-out also must be considered.

Woe to the engineer who just slaps a 100-pF capacitor across the line to solve an EMC problem. Now the delay at the 7-pF part becomes

Tpd = (77.8 × 10-9 × 148.66 × 10-12)0.5 = 3,401 ps

The same thing happens when a 300-nH ferrite bead is placed in series with the line. In this case,

Tpd = (377.8 × 10-9 × 48.66 × 10-12)0.5 = 4,288-ps delay

It may not be obvious from these calculations, but this added delay of seven to 12 times the skew requirement will increase logical failures and require rebudgeting the system’s timing. Yes, the EMC problem may be solved, but turning the system off would solve the problem just as well.

Follow-Up on Suppression Components

The EMC solution approaches used in the past on low-speed systems may cure today’s emissions and crosstalk problems but introduce signal-integrity problems that result in high-speed system failures. This is one of the primary reasons why EMC hardening should be designed into the system from the beginning, not applied after the design is completed.

This does not mean that suppression components cannot or should not be used to solve EMC problems in high-speed digital systems. It’s a matter of when and how. Five basic types of components with amplitude-frequency or amplitude-time characteristics are used for suppression: ferrites and high-frequency filters; high-frequency, low-inductance capacitors; transient suppressors and zener diodes; current limiting resistors; and shielding. Used properly, they work well, but they should not be used indiscriminately.

Except for shielding, each of these devices is inserted into the signal path and has intentional or parasitic series inductance and shunt capacitance that may result in signal-integrity problems, even the resistor. As long as the effects of this reactance on the system’s operation are understood and considered during design, suppression components can be used to reduce unwanted emissions and susceptibility.

Shielding is used for the same purposes and, from the viewpoint of signal integrity, is quite unique. Since shielding is not inserted into the circuit, it does not affect circuit operation and can be used at any time to solve emissions and susceptibility problems without impacting signal integrity. It is the only suppression technique that can be used this way.

About the Author

Ron Brewer is vice president of EMC technical services at Instrument Specialties. He is a NARTE-certified EMC/ESD engineer with more than 25 years in EMC/ESD/Tempest engineering. Mr. Brewer serves on three technical committees and, as an internationally recognized EMC authority, has made more than 185 technical presentations in North America, Europe, Asia, and the Pacific. He also has been named a Distinguished Lecturer by the IEEE EMC Society. Instrument Specialties, P.O. Box 650, Delaware Water Gap, PA 18327, (570) 424-8510.

Copyright 1999 Nelson Publishing Inc.

November 1999

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