Test During Burn-In Is a Hot Topic

An exciting view of “a world marching toward a billion connected computers being served by high-performance networks and millions of servers that are performing billions of transactions involving all types of commerce worth trillions of dollars,” was the focus of the ITC 1999 keynote speech presented by Patrick Gelsinger, vice president and general manager of Intel’s Desktop Products Group.

In this not-too-distant future, semiconductors will play an even larger part than they do today, but the twin trends of increased performance and lower cost are at odds with traditional testing methods. Higher speed, greater complexity, smaller geometries, and a wide mix of circuit types on the same device are all proven manufacturing capabilities. Missing are corresponding advances in IC test that will deliver the full cost benefits the technology promises.

Dr. Gelsinger enumerated four challenges that face IC test. “First, the cost of manufacturing test is too expensive. Second, ATE capabilities are falling further behind the device characteristics that they need to test. Third, the quality requirements are not keeping up with the device technologies. Fourth, power delivery and power testing must undergo significant changes,” he concluded.

The important elements of his message that relate to wafer probing included the following:

    Resistive shorts and resistive opens as well as stuck-at types of faults in 0.18-µm processes.

  • Vcc transient demand of tens of amps per nanosecond.

  • Underutilization of the burn-in test stage.

  • Built-in Self-Test (BIST) circuitry to reduce dependence on external ATE.


  • Standardization of testers and test programs.

  • Technical Requirements

    Resistive faults and high transient currents affect wafer probing, but they are distinct from the last three items in the list because they are relatively independent. Since different types of faults are being found in 0.18-µm devices than generally were found in larger geometry devices, the test capabilities must change to include more types of faults. There is a cost and perhaps a test-time penalty associated with this, but major disruption of the traditional IC test flow is not implied.

    Supplying well-regulated Vcc tolerant of huge current transients also is a technical problem, but one with farther reaching effects. The consequences of meeting this requirement affect the probe-card design because of the higher currents and the crosstalk that could occur between power and signal lines. The probes themselves now must carry very high currents, which implies low- resistance contacts. And because of the high-current transients, they also have to provide very low inductance. From the inductance viewpoint, cantilevered probes probably are not as suitable as newer, smaller geometry probe technologies.

    The increased current and regulation requirements extend back through the probe-card interface connections to the tester. Are traditional spring-contact pins suitable for such high currents? Does regulation need to be located much closer to the DUT rather than included as part of the power supply in the tester? Is signal integrity within the probe-card-to-tester interface compromised by the large power transients? Do power transients imply that the grouping and cabling of signals, power, and ground returns need to be changed?

    The Present Test Elements

    The last three items in the list—burn-in, BIST, and test standardization—are closely related to each other and to a few other manufacturing-test elements. Burn-in traditionally follows wafer probing and singulation and packaging, in that order. During burn-in, some slow, steady-state testing usually is done; for example, to establish operating margins. Functional test follows burn-in. BIST is a means of reducing or eliminating at-speed functional test.

    BIST

    BIST integrates many of the traditional off-chip ATE capabilities on-chip. In this way, synchronous logic, embedded memories, and some types of analog circuits can be tested thoroughly, at speed, while avoiding the need for and expense of large I/O bandwidth and huge ATE pattern memory.

    Both BIST and boundary scan are design for test (DFT) techniques. Boundary scan expands a chip’s input and output structures at the design stage to include latches and multiplexers. In the test mode, the latches are concatenated to form one or more scan chains. Test patterns are loaded serially into the scan chain(s) and the chip outputs compared with an expected response. Boundary scan, as defined by IEEE 1149.1, can sample or force data on inputs and outputs, force input data and sample output data on bidirectional lines, and selectively disable or enable each output.

    Five signals are defined within a test access port (TAP): TDI—test data in, TDO—test data out, TCK—test clock, TMS—test mode select, and TRST—test reset. Because each test pattern must be set up and the response read out serially, boundary scan generally is not capable of at-speed testing. However, it is a universal means of determining pin connectivity and can give good functional test coverage for relatively simple structures.

    In contrast, BIST supports at-speed test of certain types of circuit designs, but requires that all latches operate synchronously. Separate BIST controllers can be embedded corresponding to each memory and logic section of a large IC, with test algorithms tuned to highlight the expected types of faults. I/O limitations are overcome by generating test patterns locally on-chip, although boundary scan elements are used to select and program the BIST controllers. Each section of the chip must be able to be isolated via boundary scan-like I/O structures for the corresponding BIST controller to produce unambiguous test results.

    Although BIST is clearly a powerful test technique, it also is very intrusive. The chip designer must work with an integrated suite of development software that includes BIST tools. Some of the test structures are inserted automatically, such as the basic boundary scan circuitry. Other circuit changes depend on the specific flavor of BIST being implemented.

    LogicVision’s version of BIST, icBIST™, applies pseudorandom patterns to logic blocks. In this way, high test coverage eventually will be reached. For circuitry organized in hierarchical levels, it may be necessary to provide access directly to each level to avoid excessively long test times. icBIST also will suggest clock domain design changes if data cannot always be transferred securely across domains because of marginal timing relationships.

    Other effects of icBIST include slightly longer delays in paths with boundary scan elements, the preference for multiplexers rather than tristate devices, and larger output structures to include boundary scan capability. Some of these factors fall under the heading of good synchronous design practice. Others are simply part of the chip area overhead that has to be weighed against likely production yield and test-time improvements.

    Wafer Probe

    New types of wafer-probe materials improve test yield by providing a more reliable electrical contact between the tester and the wafer for both DC and RF signals. Probes made from these materials help reduce maintenance costs because they don’t oxidize in a high-temperature burn-in environment. This means that the number of wafer touchdown cycles between cleanings can be extended.

    Because of the drive to reduce test cost, parallel testing of up to 32 memory devices has become the norm. Jeffery Hinsky, director of marketing and electronic liaison for Electroglas, commented that “in the DRAM business today, people want to test 64 and, in some cases, 128 devices in parallel. When you consider the number of contacts that need to be made for a ×64 DRAM application, you have 5,000 to 6,000 points.

    “There are cantilevered probe systems for ×32 DRAM testing, but beyond ×32 it starts getting pretty ‘iffy,'” he continued. “Even at ×32, cantilevered probe cards are no longer the technology of choice.”

    The mechanical complexity of very high pin-count cantilevered probe cards and the need for better high-frequency performance are two factors that support alternative approaches such as an array of microminiature spring contacts or membrane probes.

    In addition, the design of wafer probers is changing to accommodate the very large forces associated with high test parallelism—100 lb on the wafer chuck and up to 1,000 lb at the spring-contact-pin/probe-board interface. Newly developed mechanically robust probe stations virtually eliminate deflection under these kinds of loads. Yield improves by maintaining consistent electrical contact throughout the test cycle.

    Parametric Testing

    According to John Bickley, director of marketing at Keithley Instruments, “By ensuring that individual process steps are within specification through parametric test, the requirements for extensive at-speed testing may be reduced. By understanding speed-sensitive failure mechanisms through modeling and doing full functional testing at the development stage, device makers can implement parametric tests that check for processing quality at those sensitive process steps,” he continued. “Once this is done, the BIST at-speed tests in production can be more like a random sampling than a rigorous check.”

    Mr. Bickley said that because parasitic capacitance and resistance associated with multilayer interconnections are increasingly limiting speed, several new tests have become necessary. The very small dimensions of wafer features require measurement capabilities below 1 µV and 1 fA. These low-level resolutions must be maintained in spite of the high throughput required to minimize test time.

    Faster, Bigger ATE

    In some cases, using a big, fast machine is the best choice. For example, RDRAM memory testing does not deal with the devices in isolation. To be completely characterized, the devices must be operated in the correct 28-W transmission line environment. Only an external tester with at-speed capability and the necessary constant-impedance connections can rigorously verify RDRAM performance.

    Conventional, off-chip ATE development is continuing, making higher speeds and more precise measurements available. However, increased pin- count due to device complexity or a high multiple test strategy, complex signal protocols, and the requirement of at-speed testing is pushing ATE cost to several million dollars each.

    A New Test Paradigm

    Although it’s tempting to opt for a single solution, semiconductor manufacturing test is too complex an issue for generalizations to be effective in all situations.

    BIST may well be a very good approach to resolving microprocessor or system on a chip (SoC) test requirements involving embedded memory, logic, and analog circuitry. The additional chip area required by BIST is a small percentage of what usually is a large chip size, and the reduction in test time easily outweighs the extra design and material costs.

    For conventional, commodity DRAM testing, BIST is inappropriate. Glenn Farris, marketing manager for high-speed memory test at Teradyne, said, “DRAMs are such a commodity product made in such high volume that if you used more than 2% of the silicon area for BIST, then you’ve defeated the whole purpose because the test cost was less than 2% of the device.

    “And, you have to have the ability to repair the devices,” he continued. “I don’t think BIST is economically feasible [for DRAMs], without taking up a lot of silicon, to both test and define the requirement to repair the device. In a DRAM device, [BIST] doesn’t make sense. I know people talk about BIST, but if you look into the economics, they don’t pan out.”

    According to Reynaldo Rincon, probe coordinator for application-specific products at Texas Instruments, DRAMs have standardized on connection pads arranged along the centerline of the die. This layout gives enough room for cantilevered probe access, even for multiples of 32 die. Probe scrub distance can be accommodated without requiring angled pads or incurring lost die costs (die that can’t be made if the chip gets larger) because the pads still lie within the die outline.

    Logic testing is a different story. Mr. Rincon said that there is no agreed plan for pad layout. Most current devices have pads around the chip periphery. That’s fine for single-site wafer probing but makes multiple-site probing difficult. With 45-µm square pads on a 50-µm pitch, there is very little room for probes, especially at the corners. Making the pads bigger or farther apart in an effort to improve probe access is unpopular because this leads to lost die and higher cost.

    Mr. Rincon commented that cantilevered probe cards will continue to be used, especially in the early stages of a product’s life cycle, because they have a much shorter lead time than other technologies and cost less. The choice of probe technology must be approached differently for production or development purposes. In production, the expected life of the probe card may be more important than its initial cost or delivery.

    Consequently, BIST and wafer-level burn-in are aimed primarily at reducing the test cost for logic devices. Logic devices were being discussed when Intel’s Mr. Gelsinger said, “We’re already burning in devices in expensive chambers, and by using DFT techniques, we can actually bring a great deal of the testing into the burn-in process itself.”

    W. L. Gore and Associates is developing special contact materials and test boards for wafer-level burn-in (WLBI). Initial W. L. Gore products embed 50-µm dia compliant, gold-plated contacts 45-µm high on a 100-µm pitch in a high-temperature elastomer the size of the wafer. The elastomer is sandwiched between a wafer and a matching test board that has its contacts in positions corresponding to the locations of power, ground, and a few signal pads on the wafer.

    In this way, the entire wafer can be powered. Because microprocessors, for example, have several hundred signal and power pads per device, it’s difficult to see how broadside (all signal pins simultaneously) functional, at-speed testing can be accomplished on more than a few devices at a time. On the other hand, if BIST subsystems are embedded on each device within the wafer, then only control and status lines need to be monitored, not the many tens of thousands of signals from all the pads on all the devices.

    WLBI test is making progress. “The three-year effort among Tokyo Electron, Gore, and Motorola has positioned Motorola to be the first semiconductor manufacturer to implement this technology on production devices without additional process steps. The WLBI process forces early failures in marginal and defective devices before they are sent to assembly plants for packaging and final test. The impact [of WLBI] will be reduced manufacturing costs and accelerated production cycle times by about 25%, based on estimates by managers involved in the project.”1

    Summary

    IC manufacturing test is on the move. New test requirements, the variety of circuit types embedded within one device, and the steady progression toward ever bigger and faster chips are technical reasons causing changes at each stage of production testing. When the very strong economic argument for reducing test cost and the short lifetimes of many device designs also are considered, it’s clear that significant changes are inevitable.

    The eventual outcome is not obvious. Initially, the most likely scenario is a fragmented one in which the test adapts to the type of device involved. For example, DRAM testing doesn’t seem to benefit from BIST, but logic testing does.

    Industry attention has been focused on the problems associated with the current test methods. It will take time, but a new, low-cost, and high-performance paradigm will emerge from the many separate efforts now gathering momentum.

    Reference

    1. Press Bulletin, W.L. Gore and Associates, Sept. 1998.

    Wafer Test Products

    Wafer Inspection System

    The Odyssey 300 is a wafer inspection system that features E-beam-based voltage contrast defect detection (VCDD) technology. At sub-0.15-µm line widths, less than 25% of device-killer defects can be identified through optical systems. VCDD can detect optically undetectable defects such as open contacts and vias, metal stringers, poly gate shorts, and copper damascene voids. On-the-fly defect image capture and storage provide real-time off-line review and inspection. Also included are simplified recipe setup, point-and-click operation, and die-to-any-die comparison. Contact company for price. Schlumberger, (408) 453-7017.

    Probe Card Interface


    The Triad™ Electrical Interface System comprises three concentric pogo


    ® towers, each of which provides up to 512 controlled impedance connections and 256 utilities. Flexibility is a key feature: any one, two, or all three of the concentric rings can be used together; multiple probe card sizes are accommodated; and a coaxial or co-planar standard electrical platform is provided. Triad suits both overhead or cabled-in applications. Benefits include balanced pogo

    contact force, increased repeatability, and compatibility with standard probe cards and multiple tester platforms. Call company for price. Cerprobe, (480) 333-1500.



    Isolated Probing Station

    The Model 2245 Automatic Test System Probing Station provides access to delidded DUTs while operating at design speeds. Features include an air-column vibration-isolating, self-leveling table; 50″ clearance under the 4,000-lb support table to accommodate automatic test systems; a motorized microscope mount with programmable 8″ X × 8″ Y × 8″ Z travel; and an 80″ W × 48″ D × 4″ H optical-quality work surface with sealed magnetic stainless steel skin. The Pentium-based system computer includes an EIA-232 interface. IEEE 488 is optional. The Model 2245 is compatible with the manufacturer’s probing products including the 900-series software or joystick controllable manipulators. From $100,000. The Micromanipulator Co., (800) 654-5659.

    Parametric Test System

    The Model S630 Automatic Parametric Test System features a noise floor below 10 fA and a 60-MHz bandwidth. A go, no-go high-frequency measurement path for ring oscillator structures provides a rapid technique to examine a fully integrated production process. Measurements on devices using copper and low-K dielectrics verify gate length, channel length, and parasitic performance of the transistors. In addition, gate oxide reliability, dielectric absorption, DRAM refresh times, and flash program/erase cycling can be characterized quickly in production. Call company for price. Keithley Instruments, (800) 552-1115.

    Copyright 2000 Nelson Publishing Inc.

    March 2000


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