Several factors drive the need for significant change in component assembly and test handling. These include the operational complexity of handling the increasingly smaller package-to-die size ratios and the economic challenge of fast-dropping semiconductor prices—especially for mobile communications. Measures to contain costs and new handling technologies to manage ultralight-weight components and improve efficiency are urgently needed.
One solution is a new matrix approach to end-of-line processing that uses standard leadframe strips to integrate massive parallel assembly and testing. This high-density leadframe (HDLF) process was developed by Amkor Technology and implemented in a joint effort with Credence Systems. Using this approach, Amkor has reduced capital cost, floor-space requirements, and index time significantly while improving quality and cycle times.
Conventional Assembly and Test
Most ICs are handled serially following fabrication, a process that increases the complexity and cost of parts handling (Figure 1, see July 2000 issue of EE). Identical package types from different manufacturers frequently have slight dimensional variations due to differences in molds and materials. Component testing also can be delayed for weeks waiting for test handler/interface kits
Inefficient end-of-line handling also makes guaranteeing lot integrity (tracing finished units back to a single wafer run) and data integrity difficult because a programmable location must be assigned to each die. This involves time-consuming manual handling or optical marking and sorting and may not be possible for small chip-scale packages or micro ball-grid arrays (µBGAs).
Advanced packages also have been reduced in size and weight so that conventional transfer by gravity feed or vacuum pickup now is less reliable and too time-consuming relative to test time. Without encoding, data integrity is lost the moment devices are tested out of order.
Matrix Processing
MatrixTM or strip processing tests devices assembled in standard or HDLF strips. The technique incorporates the test module as part of the assembly line to eliminate serial handling and attendant inefficiency (Figure 2).
By using standard strip-handling tooling and robotics, Matrix processing leverages the capability to test many parts in parallel. This minimizes index time and the risk of damaging discrete parts during conventional singulation testing and handling. Essentially, any chip that can be parallel tested at wafer sort can be tested by the Matrix technique (Figure 3).
Figure 3.
Improved Productivity
Efficiency lost by switching from parallel to serial processing can be estimated by multiplying the unit process time by the maximum number of units that can be handled by a parallel operation.
For example, a test handler transports a tray of singulated devices to a carrier, where the devices are moved through the test chamber and contactor area. Loading the carrier may require 500 ms per device or 8 s for a 16-site parallel handler. The carrier itself may take 2 to 3 s to be positioned on the test contactor. If it takes 10 s for these activities and a pipelined architecture in the handler, the shortest test time that the parallel handler can support is about 10 s per batch of 16 devices.
Conversely, one strip of devices can be moved in about 1 s. Movements for operations involving only part of a strip take about 300 ms. Larger movements, such as moving the strip into the test-contactor area, require about 2 s. Using the simple example of a 16-site parallel handler, the Matrix process supports test times shorter than 2 s vs. 10 s for non-Matrix testing.
Parallel testing now can reduce the cost of testing devices that have relatively short test times. Key deciding conditions for moving to Matrix test include high-volume production, lower lead-count packages, ease of parallel test at wafer sort, and data-tracking requirements.
Previously, only devices with long test times, such as DRAMs and large flash memories, could benefit from parallel handling because their testing time exceeded the load and index time of the serial-to-parallel handlers. Since many of the lowest-cost devices have short test times, Matrix testing can bring the cost advantages of massive parallel testing to this market segment.
Lot and Data Integrity
In Matrix testing, all devices are secured on one strip and can be precisely registered with the lot ID encoded on the Matrix margin. Not possible with singulated testing, this tracking capability enables the use of strip maps. Strip maps are similar to wafer maps generated at wafer probe and can support assembly troubleshooting and statistical process control. Existing data-handling software currently used for wafer mapping and yield analysis often can be adapted to provide Matrix map data.
For instance, if one site on a test system is yielding erratic results, the Matrix process traces the individual units back to the test site in question. This can be accomplished physically if the strips have not been separated or if strip maps are used. Tracking also speeds debugging to improve assembly yield.
Data tracking can lower costs. For products such as microprocessors, which typically contain special internal programmable devices for tracking, this can be a significant advantage. Identification now is on the leadframe, not taking up valuable circuit space.
Handling
With Matrix processing, ultralight-weight packaging now can be handled more efficiently. Only one precision alignment step is required for an entire strip of devices instead of one for each unit. This advantage not only affects testing, but also the handling for marking, inspection, and any process that requires precise package alignment.
Full Test at Wafer Sort
In addition to improving end-of-line economics and simplifying process troubleshooting, the traceability of Matrix processing enables full test at wafer probe when coupled with recent advances in wafer test technology. Tests that formerly could only be done on packaged parts now can be performed at wafer probe. This eliminates the need to perform these tests after assembly.
The capability provides more process data to IC fabricators for increased parametric quality sorting prior to assembly. In assembly, it simplifies testing of packaged parts to 100% or near-100% testing to verify the assembly process.
Challenges and Issues
Because Matrix processing uses standard strip-handling robotics and a modular assembly and testing line, it is straightforward to reproduce anywhere once the process has been developed. The challenges of implementing the technique, however, need a cooperative effort among suppliers and users because Matrix testing requires Matrix assembly. This involves chip suppliers, test-equipment vendors, robotics designers, and assembly and test houses.
One key requirement is achieving electrical isolation of devices in the leadframe assembly strip while still maintaining a physical connection to the leadframe. Designing a flexible test module that can accommodate a variety of carrier strips is another requirement since specifications for different packages and lead counts will vary.
Addressing the high mechanical force problems associated with connecting multiple pins is a technical concern in Matrix testing. In addition, dissipation of the heat generated by multisite testing must be managed. Finally, device-specific electrical isolation strategies to minimize crosstalk between adjacent parts must be determined.
Matrix Test at Amkor
Since February 1999, Amkor has been using Matrix testing in volume production. The company currently tests 50 nonvolatile memory components in parallel using 70-mm leadframe strips, Credence testers, and Fico handlers. Amkor has used the strip-mapping capability to improve device quality and experienced an increase of 1% to 3% on overall test yield. Plans to develop Matrix testing on several new products currently are in progress and expected to be in production throughout 2000 and early 2001.
Conclusions
Matrix processing is the first significant step in providing a cost-effective alternative to traditional, inefficient mixed parallel and serial assembly and testing. The Matrix format also is a key enabler in shifting toward full testing at wafer probe coupled with a simplified test at the package level.
The process to implement the Matrix test will require changes throughout assembly and test. Manufacturers will have to resolve bottleneck problems with modular and integrated equipment to provide an efficiently synchronized process.
We believe Amkor has been the first to adopt Matrix testing because of the tremendous growth of the flash memory market and the emergence of new flash suppliers. We expect this segment will make Matrix testing the de facto standard within the next 12 to 18 months.
About the Author
Paul Sakamoto is vice president of the Memory Products Business Line at Credence Systems. Prior to joining the company in 1995, Mr. Sakamoto held several sales and engineering positions including vice president of sales at Micro Component Technology and director of sales development at Megatest. The 22-year veteran of the semiconductor industry received a B.S.E.E./C.E. from Oregon State University. (510) 623-4775, e-mail: [email protected]
Andrei Berar is vice president of system integration at Credence Systems. Mr. Berar also has held management positions at Teradyne and Electroglas. He earned an M.S. degree in mechanical engineering from the Politechnical Institute in Bucharest, Romania, and an M.B.A. from Pepperdine University. (510) 623-5189, e-mail: [email protected]
Credence Systems, 215 Fourier Ave., Fremont, CA 94539, www.credence.com.
Miles Prim is vice president of worldwide test at Amkor Technology. He has 23 years of experience in semiconductor operations and international manufacturing management. Previously, Mr. Prim served as vice president and general manager of Amkor’s Philippines operations and as senior director of worldwide manufacturing for semiconductors at Western Digital. Amkor Technology, 3200 W. Germann Rd., Chandler, AZ 85248, (480) 821-5000.
Published by EE-Evaluation Engineering
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July 2000