Device Models for ESD Testing

We all have concerns when it comes to devices being subjected to ESD, the silent killer present in every semiconductor factory throughout the world. We know with absolute certainty that ESD cannot be eliminated, but it can be controlled.

The first step in dealing with this enemy is to identify what ESD thresholds your product can withstand and what kind of controls are needed. At ON Semiconductor, we perform three different ESD model tests to identify the threshold for every device manufactured. Not only is this helpful in our efforts to combat ESD, but it also lets our customers know the ESD voltage limitation for every device.

The tests are required as part of the qualification process before any device under development can be released to production. If the withstand voltage is too low, the device may require a redesign to bring it to an acceptable level.

Human Body Model

Human body model (HBM) testing simulates the discharge of ESD from the fingertip of a human being. Using a Verifier V2 System with voltage capabilities up to 8 kV, we apply voltage pulses as specified in the Automotive Electronics Council document, Stress Test Qualification for Integrated Circuits (AEC-Q100-002-REV-C, Oct. 8, 1998).

The testing is tailored to our customers’ applications following at least the standard minimums. The most widely accepted ESD withstanding voltage is 2,000 V. This is the minimum voltage a device must withstand and still operate within specified limits.

Since the AEC standard, which also encompasses ESD Association S5.1-1998 and JEDEC EIA/JESD22/A114, does not allow skipping of voltage levels, we zap devices with 500, 1,000, 1,500, 2,000, and 4,000 V. We sample at least three devices per voltage level.

The 4,000-V level helps us improve protection beyond our customers’ needs. Occasionally, we test between 2 kV and 4 kV to find out just how much the devices exceed the 2-kV level.

For example, the results of HBM withstand voltage testing on LCX Low-Voltage CMOS Devices are shown in Figure 1. Beginning in February 1996, the failure rate decreased although the failures that did occur were fully 1,000 V below the minimum 2,000-V requirement.

In January 1997, the device was replaced by a redesigned part with a smaller geometry. The failure rate from January 1997 until November 1998 remained about the same as during the previous period, but the failures that occurred were only 500 V below the required level.

Machine Model

Machine model (MM) testing simulates ESD that may occur through contact with a machine or mechanical piece of equipment. Using the Verifier V2 System with 800-V MM capability, we apply voltage pulses as specified in Attachment 3 of AEC-Q100-002-REV-C.

Since testing typically has shown a direct correlation of results between HBM and MM withstanding voltages (10:1 respectively), we vary from the specification by starting at 100 V instead of 50 V unless a customer directs otherwise. In addition, we zap three devices minimum per voltage level at 200 V and 400 V. The most widely accepted ESD withstanding voltage for MM testing is 200 V.

The AEC attachment takes into account the requirements listed in ESD Association S5.2-1994 and JEDEC EIA/JESD22/A115. While MM testing is performed at lower voltage levels than HBM testing, it actually is a more stressful test because it does not have the same resistive values as used in HBM testing.

Charged Device Model

Charged device model (CDM) testing is a simulation of the phenomenon that occurs when a device accumulates a charge through friction with packaging materials or automatic handling equipment. When the device contacts a grounded surface, it discharges rapidly to ground. Since this event happens extremely fast, the ESD protection circuitry does not have time to react, and the device can be damaged.

Although this type of testing has not gained industry-wide recognition, we provide CDM testing for our customers. Other than internal ON Semiconductor standards and specific criteria given by customers, we adhere to ESD Association S5.3-1996. Because the specification does not designate that every voltage must be performed or in what order, we zap the devices at 1,500 V first and, after testing, continue to test backwards at 1,000 V and 500 V until a withstanding voltage is found.

We use a Verifier CDM System and a nonsocketed, dead-bug, field-induced method outlined in the ESD Association standard. Atmospheric aspects of the environment such as humidity, light, and dust are well controlled within this system.

Significant precautions are taken during testing to ensure that the devices are not charged before beginning the test. This type of testing is extremely useful in tracking ESD problems that may be associated with testing materials and storage cases.

As die geometry shrinks and susceptibility to ESD increases, maintaining an acceptable threshold becomes more challenging for device designers. The introduction of smaller packages creates new requirements and specialized handling techniques for traceability of the individual devices as they go through the various qualifications.

Proper identification of every device is essential in the event that a failure occurs. The devices must be tested prior to receiving any ESD testing and the data stored for comparison with the data after the devices have been zapped.

About the Author

Michael Hoogstra works in the New Products Development Group for ON Semiconductor. The 19-year veteran of the company is a former ESD coordinator and former vice president of the Arizona Chapter of the ESD Association. Mr. Hoogstra earned a degree in electrical and electronics technology in 1981. 602-244-3851, e-mail: [email protected].
Michael Jones has been a test technician and software developer in the New Product Development Evaluation Lab at ON Semiconductor for the last five years. He received training in electrical engineering and computer science from Arizona State University and currently is pursuing a bachelor’s degree in information technology from the University of Phoenix. 602-244-3818, e-mail: [email protected].
ON Semiconductor, 5005 E. McDowell Rd., Phoenix, AZ 85008.

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Published by EE-Evaluation Engineering
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September 2000

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