Strict quality mandates relative to manufacturing test combined with the enormous complexities of today’s systems-on-chip (SOCs) demand new approaches in design for testability (DFT). This can be expressed as a requirement to achieve DFT closure—the capability to rapidly, predictably, and repeatably satisfy all mandated design and test requirements. Successfully achieving DFT closure is critical in today’s SOC designs and driving every tool in the design flow to become fully aware of testability.
SOC design flows requiring discrete handoffs between design phases are quickly becoming obsolete. To date, timing closure has been the driving force in integrating design processes into more unified flows. For example, physical synthesis technologies are quickly being adopted because integrating the synthesis and placement processes can offer drastic reductions in the design iterations needed to achieve timing closure.
The goal to achieve rapid timing closure drives design tools to accommodate all factors related to timing. Likewise, DFT closure is driving the incorporation and integration of testability into the design tools. Although timing closure has been a primary goal for designers, in many ways it is a subcomponent of DFT closure—final SOC timing must be met for a design with all test logic in place and verified.
Only recently has this last requirement been acknowledged as the real problem to solve. While test synthesis is ubiquitously used in conventional ASIC design flows to implement DFT, it is quickly becoming evident that testability must be addressed throughout the entire design flow. To successfully meet all the design goals of enormously complex SOCs, new design and DFT technologies must be deployed to enable swift and simultaneous convergence of all constraints: function, timing, area, power, reliability, routability, and testability.
Achieving successful DFT closure requires that designers in all phases of the design flow, from register transfer level (RTL) to layout, work on a unified view of the design, using integrated tools and flows. Since timing is critically important, achieving DFT requirements must not impact timing closure. This wide-ranging view of testability is supported by new technologies:
- Consistent, comprehensive, and integrated DFT analysis beginning at RTL.
- Physical synthesis capable of automatically and directly implementing all DFT architectures with full constraint optimization and complete awareness of test-mode behavior and requirements, such as clock domains, capture groups, and optimal scan routing.
Completely automated creation, verification, and management of test design data such as design database attributes, initialization sequences, protocol information, and vector files.
Why Is DFT Closure Important Now?
DFT closure is being able to meet all mandated DFT requirements through every phase of an SOC design flow, with no risk of design iterations caused by unanticipated test impact. As ICs get more sophisticated, not embracing a reliable DFT closure methodology will result in designs that may miss market windows and still fail to meet required functionality, performance, and manufacturability goals.
DFT closure assumes a top-down hierarchical design approach that predictably proceeds from RTL, presynthesis planning all the way to physical implementation. Traditional over-the-wall methodologies requiring design handoffs between discrete processes, such as between synthesis and scan insertion, are becoming intractable. Ignoring integration issues between discrete design processes in over-the-wall approaches can lead to schedule-killing iterations.
Figure 1 depicts an over-the-wall gate-level DFT flow with many iteration loops due to the likelihood of finding problems later in the design flow. In this approach, there are numerous opportunities for the designer to unknowingly break DFT rules, incurring unacceptably long iteration loops to fix problems.
To avoid this situation, each design process in a more robust flow must follow new rules:
- Each design process must be self-contained. It cannot rely on a subsequent process to completely satisfy its goals.
- Each design process must perform its task with full understanding of the requirements of the subsequent process and transfer only valid information to it.
For example, today’s design tools and flows all strive to achieve timing closure. Advanced design flows using common timing engines which can forward-annotate timing constraints from high-level design to physical synthesis can eliminate many design iterations and enable huge productivity gains in complex SOC designs. DFT closure needs to be achieved in the same fashion: completely in parallel, because these SOCs also must be testable.
By applying these rules in a DFT context, Figure 2 illustrates the benefits of an up-to-date test synthesis-based design flow. The long iteration loops from the lack of DFT knowledge between synthesis and separate test activities are partially eliminated. Design-flow closure is achievable when these requirements are met for all steps in the flow.
Finally, a new design flow supporting complete DFT closure also requires that:
- Each design process is aware of all relevant DFT issues and able to meet all relevant design and DFT requirements simultaneously.
Each design process transfers only DFT design-rule correct databases to subsequent processes.
The Road to DFT Closure
Achieving successful DFT closure is a process that will evolve and strengthen as new tools and methodologies are presented to the market. With existing technology, it means implementing a flow that satisfies all design requirements in a predictable manner, without excess design iterations and wasted designer effort.
In addition to the required intelligent, up-front planning of design and test architectures and design flows, key design and test technologies must be deployed as well, including:
- Test-enabled RTL code checking.
- In-depth RTL DFT design rule checking (DRC), analysis, and verification integrated with design synthesis and consistent with downstream test synthesis and automatic test program generation (ATPG) tools.
- Comprehensive test-synthesis capabilities within a timing closure flow.
- DFT links to physical synthesis, placement, and routing.
- Synthesis- and gate-level manufacturing testability analysis.
- Design tools sign off to ATPG.
- ATPG sign off to vector validation and production test.
Each of these technologies contributes to DFT closure by enabling completion of all relevant design and test tasks within a single process and transferring complete and valid design data to subsequent processes. By doing so, designers can eliminate the risk of long iteration loops between processes. Figure 3 shows the benefit of each of these technologies in enabling DFT closure in a design flow.
DFT Closure and SOC Test Reuse
Test tools that enable DFT closure offer other benefits as well. Provided they are truly automatic and transparent to the user, scan synthesis tools make it easy for the designer to implement test without learning the intricacies of test engineering.
Implementing scan during synthesis also means that designers on different teams, working on different blocks of a complex design, can individually be responsible for the testability of their subdesigns and know the whole device will be testable when it is assembled at the top level. This is especially important for companies that have embraced design reuse and are using predesigned intellectual property (IP) cores and following new core-based design flows. Truly automated scan synthesis tools are critical in these new IP-based design methodologies to enable DFT closure for the most complex SOCs.
The ultimate goal of implementing strong DFT methodologies is to enable the very best results and productivity in the manufacturing test environment. Implementing DFT closure to eliminate iteration loops between the entire design activity and the test floor is the next logical step.
However, with the existing over-the-wall relationships between design and test, achieving effective DFT closure between these two will be challenging. The catalyst for change will be the type of paradigm shift that now enables DFT closure in the design flow.
DFT awareness must be built directly into ATE, and ATE requirements must be built directly into design and DFT tools. Design, DFT, and ATE must conform to common standards, methodologies, and prenegoti-ated requirements. This will eliminate many of the inefficiencies incurred by the many design and data transfers that now are a requirement.
Once this is accomplished, the industry will realize additional benefits in improved productivity, lower cost, and minimized designer impact. Comprehensive DFT closure also can enable the development of a new class of DFT-aware ATE, which can lead to further reductions in the cost of test.
Great progress is being made in providing DFT closure flows to the design community, but more work remains. As IC design flows evolve to solve timing closure and verification bottlenecks, test tools must keep pace so the design community can rapidly achieve DFT closure. At the same time, testability must begin to cross over from the design world and link to the ultimate environment for testability—the hardware tester.
About the Author
David Hsu is a group marketing manager in the Synopsys Test Automation Group. Before joining the company in 1995, he was an R&D manager at Compass Design Automation. Mr. Hsu received a B.S.C.S. degree from MIT, an M.S.C.S. from Stanford, and an M.B.A. from Santa Clara University. Synopsys, 700 E. Middlefield Rd., Mountain View, CA 94043, 650-584-1658, e-mail: [email protected].
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