With the digital subscriber line (DSL) industry growing at an explosive rate, system manufacturers are challenged by the need to build and ship products as quickly as possible. Performance, compliance, and reliability are critical for telecommunications equipment, but the rigorous verification and testing processes that guarantee these requirements can sacrifice manufacturing throughput.
Programmable digital signal processor (DSP)-based solutions help accelerate and simplify verification and testing by performing many of the signal-analysis and generation functions in software. A programmable solution also allows manufacturing tests to be customized to individual system requirements and test equipment. These features translate into reduced manufacturing time and cost and increased reliability.
The Manufacturing Test Cycle
Typically, the manufacturing verification process for complex systems like DSL modems requires three stages:
- In-circuit testing (ICT).
- Parametric testing.
- Functional testing.
ICT takes place before power is applied to the board. This stage ensures that the correct components are mounted on the board with the correct orientations, the solder joints are reliable, and there is continuity through the traces. ICT typically is performed with a multiprobe bed-of-nails tester, supplemented by visual and X-ray inspections.
Parametric testing applies power to the board to check signal integrity at critical points in the circuit. While ICT verifies that all components are properly placed on the board, parametric tests confirm that the analog design meets the performance requirements by detecting subtle manufacturing faults. These requirements are based on industry-standardized and vendor-prescribed specifications and test topologies and designed to ensure proper modem performance.
Among the essential parameters tested are power spectral density (PSD), transmit and receive linearity, filter frequency responses, and noise characteristics. Most parametric test stations often are bed-of-nails testers and provide tip/ring (T/R) connections through the system interfaces to signal generators and analyzers.
Board assembly and analog performance are verified when the unit under test (UUT) passes parametric testing. Then, the UUT proceeds to the functional test station, where the evaluation cycle generally is finished by mounting the UUT in a rack and achieving a modem connection with a central office (CO) or remote terminal (RT) pair.
Functionality is determined by measuring connection rates and passing data traffic to verify the digital back end. To minimize variables, functional testing generally uses known-good or golden modems and equipment from various manufacturers to ensure interoperability.
Often, the functional tests use built-in self-tests (BISTs) and various loopback modes to supplement these tests. The details of these vary among individual chipsets but are useful in both testing and debugging faults.
A Time-Consuming, Cost-Critical Process
Details of the different testing stages vary depending on the individual system designs and test equipment. However, due to the many specialized types of equipment required, the testing process can become cumbersome, time-consuming, and costly. Since the tests performed in each stage are so different, each stage requires its own test station or stations.
In addition, the physical handling involved in moving each board from station to station not only is labor-intensive, but also a potential problem since it increases the possibility of introducing human errors into the testing process. Minimizing test equipment and space, improving quality control by less UUT handling, and reducing test time for each board translate into per-unit manufacturing cost savings and improved ramp-up times for high-volume production.
The Programmable DSP Advantage
Programmable DSPs, which play an increasingly important role as the high-performance processing engines for DSL systems, can help DSL manufacturers attain their cost and time objectives. By leveraging the programmable DSPs and analog front ends (AFEs) found in asynchronous DSL (ADSL) chipset platforms, system manufacturers can replace dedicated test equipment with functionality embedded in the chipsets. This is accomplished by leveraging the DSP to perform many of the complex signal-generation and analysis functions currently implemented in external test equipment.
A DSP-Based Testing Example
An illustration of how DSPs support advanced manufacturing testing is found in a CO line-card design based on the Texas Instruments AC5 DSL Chipset. As shown in Figure 1, the eight-channel AC5 Chipset consists of the following devices: a digital ADSL transceiver engine that integrates a programmable DSP; a programmable Advanced RISC Machines (ARM) microcontroller, framing logic, and memory; a mixed-signal AFE that integrates data conversion, coding-decoding, filters, and various other functions; and eight single-channel line transceivers.
In addition to integrating BISTs for both ICs, the AC5 platform features test utilities that check the continuity and signal integrity of digital interfaces within the system at power-up. This functionality supplements and may substitute for some of the usual trace checking performed in ICT. The integrated Joint Test Action Group (JTAG) test port in each device provides visibility into these utilities, allowing them to be used for bench-level tests and field diagnostics as well as system self-tests.
The DSP’s capability to generate and analyze signals is most beneficial in the parametric testing stage. This capability potentially eliminates a very expensive and time-consuming step of traditional parametric test stations because the elaborate array of probes on a bed-of-nails tester no longer is necessary.
Instead, manufacturers can mount the DSL line card directly in the end equipment such as a DSL access multiplexer (DSLAM) chassis, then use the existing T/R interface from the backplane to interconnect to necessary test equipment, as shown in Figure 2. The test software is controlled via the normal system management console. The DSP runs parametric tests and delivers pass-fail results in seconds. In addition, some test equipment manufacturers include support for DSP parametric testing in their systems, helping to make the DSP’s signal-analysis capabilities an automatic part of the testing environment.
Self-contained tests validate the transmit and receive signal paths from the DSP to the hybrid circuit based on programmable thresholds. For these tests, the DSP functions as both a signal generator and a spectrum analyzer and can measure both transmit and receive channel responses. For example, to verify transmit performance and compliance, the DSP generates a test spectrum that can be analyzed at the T/R interface for spectral compliance, channel linearity, and filter shapes by an external spectrum analyzer.
In addition, with a signal injected at the T/R interface, the DSP can analyze the receive channel’s filter shape, gain, and noise performance. All parametric tests also provide detailed results to aid in fault isolation and resolution.
Traditional bed-of-nails testing only checks parametrics from the hybrid circuit to the codec, but with the ever increasing IC integration, many of the AFE elements such as filters are inaccessible to external probes. This test limitation does not exist when using the DSP because the codec and its signal chain now become accessible.
In implementing this functionality, the AC5 Chipset provides a number of built-in parametric test functions including reverb, missing tone, return loss, and idle channel noise and receiver response tests. It also performs sophisticated algorithms that require specialized DSL external test stations.
Programming Flexibility
DSP programmability also allows manufacturers and test engineers to write software for additional tests, depending on individual requirements. For instance, tests might be added to validate other hardware on the board, add parametric tests, or check for specific line conditions in the local loop in a field trial.
The system can be programmed to perform functional testing, which can take place at the same station as the parametric tests, saving handling and equipment costs. Since the ARM microcontroller serves as the management controller for the DSP, manufacturers have a familiar processor environment to work with when building high-level software interfaces such as scripting languages.
Reducing Test Time and Cost
As DSL systems ramp to volume and revenue margins become critical, it becomes increasingly important to reduce manufacturing test costs to maintain product quality and reliability. Programmable DSPs provide a key technology for accelerating and improving this process as well as other areas of evaluation such as prototype debugging and field-testing. The same programmable DSP engines that drive DSL systems to new levels of performance can provide greater flexibility, timesavings, and cost reductions in the manufacturing test cycle.
About the Author
Erich Vogel is a systems and applications engineer specializing in DSL systems at Texas Instruments. He obtained a B.S. in electrical engineering from the University of Nevada in 1992 and an M.S. in electrical engineering from the University of California in 1995. MS 4064, 408-879-2055.
Robert Halbach is a senior hardware engineer specializing in ADSL analog front-end design at Texas Instruments. He received a B.S. in electrical engineering from California Polytechnic State University in 1995 and an M.S. in electrical engineering from Santa Clara University in 1999. He has worked at Amati/Texas Instruments since 1996. MS 4090, 408-879-2111. Texas Instruments, 2825 N. First St., Suite 200, San Jose, CA 95134.
Ben Sheppard is a DSL marketing manager focusing on CO DSL chipset solutions at Texas Instruments. He earned a B.S. in electrical engineering from Kansas State University and has been with TI since 1995. Texas Instruments, 12500 TI Blvd., MS 8650, Dallas, TX 75243-4136, 214-480-3060.
Published by EE-Evaluation Engineering
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October 2000