Signal integrity in ATE fixture boards, also referred to as load boards or device under test (DUT) interface boards, is a key part of achieving a high-quality, low-noise test environment. At-speed testing places severe requirements on the quality of load boards, demanding minimal signal distortion at speeds of several hundred megahertz and subnanosecond rise times. Distortion of the test signals delivered to the DUT and the signals received by the tester comparators results in test errors, rejection of working parts, and, even worse, acceptance of faulty ones, costing the manufacturer thousands or even millions of dollars.
Characterization of ATE fixturing using time-domain reflectometer (TDR) measurement methodology allows more accurate production test limits to be set. Test engineers also can use detailed load-board characterization data to model device performance accurately in the test environment and ensure accurate interpretation of test results. With accurate characterization data, test engineers can improve overall test yield for their ICs, resulting in significant savings for the IC manufacturer.
Load-Board Characterization
A load board typically contains a test socket or contactor for connecting the DUT to the test system. The test socket is mounted on a controlled-impedance printed circuit board, which is mounted on an ATE test head and uses high-performance connectors to connect to ATE pin electronics. Because of the typically large pin-count of test devices, most load boards are quite complex internally, running 10 to 18 layers, including signal, power, and ground layers.
For example, the paths from the tester driver to the device pin and from the device to the tester receiver are designed in the Integrated Measurement Systems (IMS) load boards to be 50-W structures with minimum discontinuities and of equal electrical length. This design minimizes distortion as the signal propagates through the interconnects in the system.
Some of the complexity of the boards is caused by preserving the controlled-impedance transmission-line nature of the traces. To understand signal distortion as the signal propagates through the load board, all the components of the ATE load board must be characterized. Connectors and test sockets introduce small inductive and capacitive discontinuities that must be considered as well.
TDR measurement traditionally has been used to determine impedance in high-speed digital boards and is a natural choice for characterization of the ATE load boards.1,2 But, performing a TDR measurement on all the signal paths in the ATE load board is time-consuming.
To save engineering time and achieve the desired characterization results in the most expedient way, one or several critical signal paths on the load board must be chosen. Selection can be based on a visual inspection of the board layout, the designer’s knowledge of the board components, and the experience of the load-board designer. If the board is analyzed as a suspect component leading to test failures, a device pin with an unpredictable failure pattern may be the one that requires the most attention, and the load-board path to that pin can be designated as the critical path.
If the load board has more than a single impedance trace on a single board layer, the TDR measurement by itself will not provide accurate impedance measurement information because of the multiple reflection effects present in the TDR waveform.3,4 The multiple reflections are due to the re-reflection of the signal inside the load board itself between different discontinuities.
The true impedance profile (Zline.wfm) shows the connector section in the beginning of the board, the 50-W controlled-impedance section of the board itself, and the open-ended termination of the interface point. The length of the board trace now can be accurately measured as a 1.2-ns round-trip or 600-ps one-way delay. The open far end of the fixture interconnect is indicated by the impedance waveform going off the top of the screen and reaching a high-impedance value.
The impedance deconvolution algorithm is implemented in TDA Systems’ IConnect Software and applied as follows: The true impedance profile is computed from the TDR waveform and the reference short or open waveform. The reference waveform defines the reference measurement plane for the board trace under test. The impedance profile of the board, computed from the TDR measurement, reveals a well-controlled impedance DUT interface (Figure 2).
Load-Board SPICE Model Extraction
In addition to obtaining accurate impedance information, it is important to provide a complete simulation program with integrated circuit emphasis (SPICE) or an input/output buffer information specification (IBIS) model of the load-board interconnect so the signal distortion not only can be observed, but also predicted in simulations. The true impedance profile, once computed, provides an easy path to obtain such SPICE models for the load-board interconnects.
Based on the true impedance profile, IConnect can automatically save a SPICE equivalent circuit model for the critical path under consideration. Trace impedance and delay are computed directly, and parasitic inductance and capacitance can be computed from the impedance profile using the following equations:
To check the validity of the board model, IConnect allows the designer to recreate the TDR incident step for the simulation, using the reference short waveform. Recreating the TDR incident step in simulation is important to ensure one-to-one comparison of the measurement for the load board and the simulation, the latter obtained using an IConnect-generated model for the load board and the TDR source.
Once the model for the critical path is validated, the fixture designer can provide the test engineer with meaningful and accurate equivalent circuit data to predict the signal distortion in the load board. Additionally, if required by the designer, he or she can compute S-parameters for the critical path interconnect or spectrum for the signal in question. For example, S21, computed in IConnect based on the time-domain transmission (TDT) measurement, can provide information about the insertion loss of the load board under test.
Differential lines in ATE fixtures can be characterized similarly using the approach outlined in Reference 6. Even- and odd-mode impedance profiles, computed from differential- and common-mode TDR measurements, can quickly provide a distributed coupled line model from which you can accurately predict the signal integrity issues in an ATE fixture.
Connector Characterization
Connectors are key to the overall DUT board performance, since it is significantly harder to maintain controlled impedance through a connector and a connector-to-board interface than through the board itself. IMS has selected the Amp Z-Pack Stripline Connector family, specified to have a controlled impedance and low crosstalk environment up to 250-ps rise time.
To analyze the connector performance at the device-specific rise time, rise-time filtering was applied again, this time using a 175-ps filter. The impedance profile shows that the probe discontinuity is negligible and the connector exhibits controlled-impedance behavior.
The equivalent SPICE model computed by IConnect consists of a 100-ps long transmission line with 58-W impedance. This model is valid up to the 175-ps filter rise time. The equivalent 3-dB frequency range can be estimated as approximately 2 GHz, using the following equation:
Based on the reference short measurement, a designer again can recreate the TDR incident step in IConnect. Comparing the simulation results to a measurement verifies the accuracy of the model.
Test-Socket Characterization
Test-socket characterization is an important part of the overall signal-path characterization in the ATE environment, since sometimes the test-socket parasitics can be high. Socket vendors frequently provide the parasitic inductance, capacitance, and resistance data; however, it often is important to validate this data in the specific test environment.
Typically, a lumped RCL model for the test-socket parasitics is used, which is valid when the electrical length of the socket is small compared to the rise time of the test signals. The rule of thumb is to consider a model lumped if the electrical length of the interconnect segment, for which this model is developed, is about 1/6 of the rise time of the signals propagating through the interconnect. The factor of six is somewhat arbitrary but widely used by high-speed designers as a rule of thumb.
The test socket can be characterized following the procedure for characterization of electronic packaging outlined in Reference 5. Both self- and mutual inductance and capacitance can be computed using this guideline. For example, for capacitance computation, the designer will send a TDR pulse into a socket lead and acquire the DUT waveform (WTDR).
By removing the socket from the board and performing a TDR measurement on the same trace, the designer obtains the reference open waveform (Wopen). Then the self-capacitance can be computed as the difference between the two waveforms.
Mutual capacitance of the socket can be computed based on the near-end crosstalk measurements. Self- and mutual inductance also can be computed similarly to the self- and mutual capacitance. The reference waveform must be a short reference, and the socket lead under test must be shorted to ground on the inside of the package.
The fixture for inductance measurements, as defined in Reference 5, is more complex than the fixture for capacitance measurement and requires making a short connection on the inside of the socket to ground. This is why an alternative procedure may be preferred using a differential TDR modeling approach discussed in Reference 6.
Differential (odd)- and common (even)-mode TDR measurements are used to compute the full L and C matrices for a pair of the socket leads directly, immediately providing the self- and mutual parasitics information. This approach assumes that the socket leads under test are symmetric, which is true for most ATE sockets.
To achieve good characterization accuracy, the board traces leading to the socket leads under test also must be symmetric. The differential approach may be a more practical way to characterize socket parasitics when the fixturing recommended in Reference 5 for inductance characterization cannot be readily achieved.
References
- Tilden, M.D., “Measuring Controlled-Impedance Boards With TDR,” Printed Circuit Fabrication, February 1992 (Tektronix Application Note 85W-8531-0).
- TDR Theory, Hewlett-Packard Application Note 1304-2, November 1998.
- Hayden, L.A. and Tripathi, V.K., “Characterization and Modeling of Multiple Line Interconnections From TDR Measurements,” IEEE Transactions on Microwave Theory and Techniques, Vol. 42, September 1994, pp. 1737-1743.
- Smolyansky, D.A. and Corey, S.D., “Printed Circuit Board Interconnect Characterization From TDR Measurements,” Printed Circuit Design Magazine, May 1999, pp. 18-26 (TDA Systems Application Note PCBD-0699).
- Guideline for Measurement of Electronic Package Inductance and Capacitance Model Parameters, JEDEC Publication #123, JC-15 Committee, October 1995.
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Smolyansky, D.A. and Corey, S.D., “Characterization of Differential Interconnects From Time-Domain Reflectometry Measurements,” Microwave Journal, Vol. 43, No. 3, pp. 68-80 (TDA Systems Application Note DIFF-1099).
About the Author
Dima Smolyansky is a product marketing manager at TDA Systems. He has published many papers and taught short courses on interconnect measurements and modeling. Mr. Smolyansky holds an M.S.E.E. from Oregon State University and an M.S. from Kiev Polytechnic Institute. TDA Systems, 11140 SW Barbur Blvd., Suite 100, Portland, OR 97219, 503-246-2272, e-mail: [email protected].
Richard Gaunt is manager of the fixture development group at Integrated Measurement Systems. Before joining IMS, he was an engineering manager at Motorola and Tektronix. Mr. Gaunt earned a B.S.E.E. from Portland State University.
Alan Nolan has been employed by IMS for 15 years, most currently in the fixturing and interfacing group. Mr. Nolan has 25 years of experience in electronics, six years while serving in the U.S. Navy.
Integrated Measurement Systems, 9525 SW Gemini Dr., Beaverton, OR 97008, 503-626-7117.
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November 2000