The reasons are many. First, there is the issue of universality. That is, an ideal ATE system must provide a clock at any speed required by the device under test (DUT). In addition, because complex circuits have split clock domains, a number of synchronously related clocks running at different rates, or even deliberately asynchronous clocks, supplying one simple clock won’t do.
There’s also the matter of noise. The device manufacturer is trying to determine whether a product is performing properly when connected to the ATE. Especially in mixed-signal applications involving both analog and digital circuits, clock jitter can be a big problem. Is the DUT performance really marginal, or is the ATE environment causing it to appear that way?
Finally, at the heart of mixed-signal testing is the relationship among DUT driving signals, the DUT functional activity, and measurement timing. In mixed-signal testing, it makes a difference at which moment you measure the output of a DUT’s digital-to-analog converter (DAC). Clock synchronism is a major factor in making mixed-signal measurements. You will get a different, and worse, answer if the sampling clock controlling measurement timing is not synchronous with the DAC clock.
Consequently, there are three major requirements for mixed-signal ATE clocking:
- Diversity—the number and types of clocks and their relationships and programmability.
- Precision—the lack of jitter and the extent to which edges can be precisely located.
- Synchronicity—the close linkage of input-related clocks to those controlling output measurements.
Surprisingly, absolute accuracy usually is not an issue unless exact frequencies are needed to test a filter, for example. But if a counter is being tested, even though a range of clock speeds might be used, it’s the correct number of clocks that matters, not the elapsed time. In more complex circuits, the ratio of clock speeds is critical as well as their phase alignment.
Keith Lucy, a senior applications engineer at Teradyne, explained the philosophy behind clock generation in the company’s Catalyst ATE: “Users describe their desired frequencies in equation form, and the tester software determines actual clock rates and dividers. This allows you to focus on the ratios required between the analog clocks and the digital clocks rather than the exact frequencies. To avoid spectral leakage, it is these ratios that are important, not the exact frequencies of the test.”
In mixed-signal testers, edge placement often is determined by a programmable delay following a master clock. By using two pairs of delay elements, for example, you can produce two clocks that run at the same rate but are offset in time from each other and have different duty cycles.
Delays also can be used to generate other frequencies. To generate an odd frequency, such as 89.7 MHz, the leading- and trailing-edge delay generators are set to the necessary values, on the fly, at each 100-MHz clock.
Multiplexing a number of signals, each generated by delaying from the same master clock, increases effective clock speed. A tester with a fundamental clock speed of 100 MHz may use four-way multiplexing to increase the output speed to as high as 400 MHz. In this case, four delays would be used to position the leading edges of the pulses comprising the four 100-MHz signals, with another four delays to position the trailing edges. For a more detailed examination of this technique, see Reference 1.
An amount of jitter is associated with each of the delay elements, and there is a limit to the precision with which the delay time can be set. The programming complexity caused by this type of multiplexing could be avoided if the master clock simply ran at 400 MHz. It generally doesn’t because all the delays must be set on the fly, and until SiGe became readily available, there was no suitable fast, low-power, low-cost technology.
A different approach has been taken by LTX. According to Ken Lanier, marketing manager at the company, “We have a unique clocking architecture in our mixed-signal test systems that allows a continuously variable master clock. With this technique, virtually any frequency can be programmed as a pattern rate, and cycle-to-cycle jitter is lower than in alternative approaches.”
Why Clocks Must Be Synchronized
Mixed-signal testers provide analog signals required by a DUT and measure analog outputs from it. But, testers basically are digital machines, so analog signals are generated from sine look-up tables, for example, and analog measurements usually involve interpretation of Fourier transform results.
Many DUTs contain DACs and analog-to-digital converters (ADCs). Maintaining synchronism among all the clocks—the tester clock that generates an analog input, the clocks used within the DUT, and the clock that samples an analog output—is crucial.
A simple example helps show the effect of asynchronous sampling. Figure 1 (below) is a magnitude plot of an Excel fast Fourier transform (FFT) performed on 2,048 data samples. There are five sets of data points that correspond to sinusoids with frequencies from 64 to 64.8 Hz. The sinusoids were sampled at a rate of 2,048 S/s.
Figure 1. FFT Skirt Broadening Caused by Asynchronous Sampling
In real-life testing, the signal frequency would be constant, but the sampling rate might not be synchronized to the signal. Either way, unless an integer number of cycles are captured, the FFT algorithm will exhibit spectral leakage. Some of the energy associated with a frequency peak will show up in adjacent frequency bins.
In an application note that describes the types of FFT windowing available in its oscilloscopes, Tektronix stated that if an integral number of cycles match the length of the data processed by the FFT function, “then the complex sinusoids computed by the FFT will fit the data exactly and uniquely.”2 Because the FFT frequency bins will be located at integer multiples of the ratio (sampling frequency/record length), 1 Hz in the case of the example, no spectral leakage will occur when the signal frequency corresponds to one of these bins.
This relationship is one reason that ATE clocks must run at exact and programmable ratios. To describe this requirement, a more precise term than synchronism is frequency coherence. In the description of its IntegraTEST Series 20 Mixed-Signal Tester, microLEX Systems defined coherency as “a system that must have its frequency and time functions programmably related in integer-number ratios.”
Figure 2 (below) shows the type of discontinuity that exists when the end of the sampled data file and the beginning are compared for non-integer numbers of cycles. The effect of a discontinuity is well known and has prompted the development of a number of windowing functions. There are many of these functions, generally named for their inventor such as Hanning or Blackman.
Figure 2. Discontinuity Caused by Non-Integer Number of Cycles
When the sampled data file is multiplied by a windowing function, the amplitudes of the samples become zero or a small value at the ends of the sample record. This technique reduces spectral leakage and makes it practical for FFTs to be used on real-life signals.
Do windows produce the best possible results? No. Windowing broadens the frequency lobes, so if you need to use a window, you can’t expect to discern the main lobe frequency and its harmonics as precisely as if a window had not been needed. The practical effect of broadened lobes is a reduction in the level of detail that can be seen close to the lobes. So, closely spaced frequencies may appear as one broad lobe rather than two distinct ones.
Consequently, capturing an integral number of cycles is one level of synchronism that ATE manufacturers need to provide. Frequency coherency means that the analog signal being measured and the sampling clock doing the measuring have the same or closely related frequencies. Another level of synchronism that is required for similar reasons involves clocking measurement and generating instruments at a precise location within each clock cycle. This is called phase coherency.
Marc Loranger, senior director of marketing at Credence Systems, commented, “The Quartet™ family of test systems is a phase-coherent system. As a minimum, synchronization of analog and digital signals must have frequency coherency, that is, they are based on the same frequency, to minimize spectral leakage.
“By extending the system to have control of phase as well, fewer cycles need to be measured so tests can be run faster. Also,” he continued, “known error sources can be ignored because their results always appear at the same place in the frequency spectrum.”
Consider the process of sampling a digital output. Just as a logic analyzer can be clocked from the system clock when operating in the state or synchronous mode so, too, do ATE measuring instruments need to sample a digital signal at the proper point relative to clock edges and setup and hold times. If the DUT output has changed state to a 1 from a 0, then the measuring instruments should record a 1. This can only happen if sampling is closely coordinated with the clock(s) that generated the DUT signals in the first place.
“We provide a feature to resynchronize analog instruments with a digital event through pattern control, assuring exact phase alignment between the measurement instruments and the DUT,” said George Rose, an applications engineering manager at Teradyne. “This feature is key for intermodulation distortion characterization of communications devices.”
Another example is Eagle Test Systems’ mixed-signal ATE that includes eight independently programmable master clock channels. According to Kevin Baade, the company’s applications manager, “The frequency control achieved enables precise coordination between signal sources and the digital signal processor (DSP)-based digitizing units, simplifying application of DSP algorithms. Additional mathematical manipulation, such as windowing, is not required. This ensures proper placement of test signals within the target frequency bins during post-processing with DSP analysis tools.”
Trends and Solutions
Frequency and phase coherency are well-understood requirements of mixed-signal ATE systems. However, providing them at high clock speeds is difficult if not impossible today. One solution includes test instrumentation as part of the DUT. Because of the growth of the communications market, a great deal of work has been done to address phase-lock loop (PLL) testing.
“Testing PLLs, especially very high-speed ones, is one of the two most difficult things to do using external instrumentation,” said Credence Systems’ Mr. Loranger. “The test fixture and connection to the instrumentation can be a significant portion of the total error in the device. The most effective instrument would be one on the chip.
“PLL built-in self-test (BIST) is the best and most cost-effective way to overcome these limitations. The measurement instrument is extremely close to the signal source,” he continued. “Accuracy is higher because the technology used in the instrument typically is more advanced than that used in an external instrument. And because the on-chip instrument focuses on this specific test, typically the measurement time is shorter.”
The second of the difficult measurements that Mr. Loranger referred to involves the timing parameters of high-speed digital I/O pins. He sees on-chip instrumentation as perhaps the next major opportunity for on-chip test capability. It could improve digital timing measurement accuracy just as it has facilitated better PLL characterization.
Another approach deliberately provides test modes in a chip design. “Test modes effectively enable the test engineer to stop the clock and examine circuit attributes individually and with less complication,” said Mr. Baade of Eagle Test Systems. “This capability increases the test coverage while eliminating some need for sensitive, DUT board-resident support circuitry. For example, when testing the complex frequency-hopping PLLs of Bluetooth™ devices, test modes allow control of the programmed frequency and test access to measure the PLL outputs.”
Finally, before deciding you need to spend several million dollars on a very fast tester, examine the DUT test requirements carefully to determine just how large the problem really is. In a recent paper on mixed-signal RF testing, Dr. Mani Soma of The University of Washington began with the statement, “There is no satisfactory method to test a circuit or system in the gigahertz frequency range.”
Paul Patton, the director of product engineering at Advantest America, elaborated on this statement: “Even if it is possible to produce a suitable signal source/detector combination on-chip, the device yield probably would deteriorate because of the existence of the test circuit on the chip. On the other hand, a simple test circuit can be realized, but this is only useful for low-level self-diagnosis.”
In his paper, Dr. Soma discussed the challenges presented by purely analog or digital circuits and mixed-signal designs. Existing test techniques then were considered, all of which had some downside. He observed that, “even in a very high-performance RF system, only a few signals and a few subsystems actually operate at the gigahertz frequencies. All others have much lower operating requirements and thus can be tested using existing paradigms.”
The paper concluded that, given the strong interdependence among test, design, and simulation, the ultimate goal of mixed-signal RF system test should be the reduction or complete elimination of testing as a separate function. This would be accomplished through development of on-chip test generation and parametric analysis modules.3
References
- Larson, E., “SOC Designs Challenge ATE Timing Architecture,” EE-Evaluation Engineering, June 2000, pp. 20-27.
- www.tektronix.com, “Tektronix MBD: Applications. FFT: Windowing What Does it Accomplish?” 1997.
- Soma, M., “Challenges and Approaches in Mixed-Signal RF Testing,” Proceedings, IEEE International ASIC Conference, Sept. 7-10, 1997, Portland, OR.
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November 2000