In the last few years, computer processor speed has accelerated exponentially. Yet, computer memory speed has not matched expectations. We saw the mass migration from PC100 memory to PC133 memory in 1999. During that time, Intel also introduced Rambus memory to the PC industry.
In the transitions, each memory technology promised more bandwidth and performance. In theory, higher memory bandwidth will deliver better performance for the computer system.
Memory peak bandwidth is defined as memory bus width ÷ 8 bits × data rate (Table 1, see below). That translates into how quickly your 3-D games will react, how cleanly your MP3 music will play, or how smoothly a motion picture will run in your MPEG video streaming.
Table 1. Peak Bandwidths for Various Types of Memory
(row access time)
This year, a type of memory called double data rate (DDR) has shown up in the new PCs. Although it is a mystery to most users, it is the result of more than three years of industry collaboration involving hundreds of top memory and system design engineers. This new kind of DDR memory is promising yet more memory bandwidth and performance at prices lower than Rambus memory.
What Is DDR?
DDR is very similar to the normal synchronous DRAM (SDR). SDR evolved out of the standard DRAM.
The standard DRAM receives its address command in two address words. It uses a multiplex scheme to save input pins. The first address word is latched into the DRAM chip with the row address strobe (RAS). Following the RAS command is the column address strobe (CAS) for latching the second address word. Shortly after the RAS and CAS strobes, the stored data is valid for reading (Figure 1).
The SDR combines a clock with the standard DRAM. The RAS, CAS, and data valid are enabled on the rising edge of each clock cycle. Due to the clocking, the position of the signals now is very predictable. Consequently, the data latch strobes can be positioned very precisely.
Since the data-valid window is very predictable, the memory can be divided into four banks to allow internal-cell pre-charge and pre-fetch. Burst mode also is added to allow consecutive address fetching without repeating the RAS strobe. A continuous CAS strobe would bring out consecutive data as long as it is from the same row.
DDR memory is very similar to SDR except that data is read at both the leading edge and the falling edge of the clock. As a result, a single frequency clock can result in a data transfer as fast as twice the frequency of the clock. The new generation of DDR memory is running at 200-MHz and 266-MHz data rates corresponding to clock frequencies of 100 MHz and 133 MHz.
How Can I Test DDR?
Although DDR memory is similar to SDR, doubling the data frequency presents a challenge to the test engineer. The tester not only has to latch the data read at twice the frequency, but also has to provide the write data at twice the speed. Two areas of DDR testing lead to separate test requirements:
DDR chips are tested at the wafer-probe and the final-package levels. The tester usually is a memory ATE. Typically, it costs several million dollars and is constructed as a fine time resolution (100-ps to 1-ns step), programmable signal generator.
The engineer can program the tester to simulate the actual operational environment. He also can tweak the timing edges back and forth to find the falloff point.
• An ATE system does have a drawback. The amount of arbitrary waveforms it can generate is limited by its backup-memory Shadow RAM and its algorithm generator. Depending on the depth of Shadow RAM, the waveform has to repeat its own cycle. Since DDR has twice the speed and bandwidth of the normal SDR, the waveform generation will require twice as many transitions.
Shadow RAM can be quickly consumed. Engineers found that they have to either upgrade their testers for more memory or stand the chance of compromising test resolutions.
• Test-head building can be a complex issue. Since the data-read window of the DDR memory is only 1 to 2 ns, pin-driver rise and fall times become critical. Better slew rate is required on the pin drivers to ensure the signal transition will be at the center of the data eye.
• Transmission-line reflection gets into play at 266 MHz. Engineers must follow stricter rules in designing test platforms. Transmission-line simulations have to be done on the test-head layout to ensure signal integrity. Pin-driver strength also has to be scalable to minimize high-frequency signal reflections.
Figure 2 (see March 2001 issue of Evaluation Engineering) shows the details of such a simulation. Signal-integrity analysis must be simulated to assure that signals fall within the good data eye.
• Design for Testability (DFT) is preferred but not adopted. Since test time and cost on an ATE system are proportional to the number of megabits on the memory chip, it becomes very costly to test larger DDR chips. The push to develop universal DFT features for the new DDR chips attempts to incorporate internal nodes that are sufficiently controllable and observable.
Specific DFT techniques including parallel test modes to test multiple arrays simultaneously were proposed by JEDEC, the industry standards committee. Unfortunately, they were not adopted due to the extreme emphasis on chip die size. DDR was viewed as a commodity that must have minimum die size for price competition.
When it comes to memory-module testing, the requirements are different. The DDR module manufacturers assume that the DDR has been tested for semiconductor failures at the chip level. As a result, they concentrate on functional exercise and assembly errors. With the new DDR dual in-line memory module (DIMM) and small outline dual in-line memory module (SODIMM), we will likely see three different approaches for memory-module testers:
• The two-passes-read DDR tester. This probably is the easiest tester to build. Most tester companies would make slight modifications on existing SDR testers to come up with this quick-to-market DDR tester.
In the write mode, an SDR tester would write identical data onto two consecutive bits of DDR memory. In the read back, the SDR tester would first read the odd-bit data (every other bit) from the DDR module. Then it would run a second pass to read the even bits by shifting the data latch by half a clock period. Essentially, this will allow the tester to completely access all the DDR memory cells. This kind of test method cannot include true burst test and is not a real cycle-time test.
• The tester with a real-time controller. It is not difficult to design a DDR tester using a real-time ASIC controller. After all, new ASIC blocks have demonstrated that they can easily reach the required frequency of 266 MHz. However, due to the volume of testers and the price-competitive market, the field programmable gate array (FPGA) is the preferred logic core for cost/volume justifications.
Building a 266-MHz memory controller on an FPGA is a challenge because it will take the latest 0.18-micron line-width chip to achieve the performance. Even though 0.18-micron chips are available, the synthesizing programs are not yet fully debugged. A close working relationship with FPGA vendors is necessary to overcome the hurdles. This kind of tester not only will be low cost, it also will provide test speed and accuracy.
• The native-environment tester. Regardless of the other test methods, memory-module manufacturers always are looking for the ultimate motherboard simulator. They believe the best test would be done on the motherboard under the actual operational environment.
However, the manufacturers also know that there are inherent problems on the PC motherboard that prohibit it from being used as a tester. The problems are attributed to slow boot time, slow test-execution time, and the relatively short life of the memory-module sockets.
Through technological breakthroughs, these problems can be overcome with a special hardware and software design. New native-environment DDR module testers will be built with X86 processors and PC chipsets. They will take away the slow boot time by implementing special test operational systems and combine cache execution with a special software algorithm to time-out the DIMM sockets. That means you now can change the device-under-test module without physically powering down and rebooting the system.
The tester will not be in the form of a motherboard. Instead, it will be laid out like a tester with the optimized convenience of a tester. It also will have a heavy-duty test socket for insertion durability.
DDR DIMM Test Handling
Most of all, a good memory-module tester needs a compatible automatic handler to complete the production solution. Conventionally, a memory-module handler uses a gold-finger contactor to make electrical probe contact with the memory-module connection taps. At the 266-MHz DDR frequency, the 2-in. long contactors would degrade the signal and introduce measurement error.
A new class of automatic handlers with direct-socket testing uses the normal test socket found in manual testing. The handler gently punches the module under test into the test socket, simulating the normal hand-insertion action. The module then is tested and gently withdrawn from the test socket.
The DDR test transformation is evolutionary instead of revolutionary. JEDEC is not standing still on this technology. Instead, it has a roadmap for further development of DDR memory.
In the path will be DDR333 for the 2002 time frame and then DDRII in 2004. The physical package also will be migrating from a thin small outline plastic package (TSOPII) to flip-chip ball grid array (FBGA). Memory test engineers will have to work through these changes.
About the Author
Cecil Ho is founder and CEO of CST. Previously, he spent more than 14 years as a design/program manager at Texas Instruments and General Instruments. Mr. Ho is an active member of the JEDEC committee setting memory standards and Advanced Memory International, an organization addressing next-generation memories. He has a B.S.E.E. and postgraduate credits from the University of Texas. CST, 2336 Lu Field Rd., Dallas, TX 75229, 972-241-2662, e-mail: [email protected].
Published by EE-Evaluation Engineering
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