Over the past 10 years, the DRAM market has been one of the toughest commodity businesses in the electronics industry. Bit growth has averaged more than 60% per year, but at the same time, cycles of over-supply have driven down the price of these bits at annual rates of 30% and higher.
Historically, the primary driver of growth in the DRAM market has been the personal computer (PC), which as of 1999 accounted for more than 60% of the bits consumed. Manufacturers looked to the next operating system release or, better yet, the next killer app, to drive PC customers to double or quadruple the memory in their desktop systems.
The dramatic changes taking place across the electronics industry with the growth of digital communications and consumer applications now promise to change the landscape of the DRAM market as well. Semico Research in Phoenix, AZ, predicts that by 2005, DRAM consumption by these communications and consumer applications will grow at nearly double the rate of the computer-related applications, achieving nearly 55% of the market by 2005 (Figure 1).
This shift in end use will be accompanied by significant changes in other aspects of the DRAM market. New applications to support these non-PC markets will have differing requirements in bandwidth, density, and power consumption. This will drive the DRAM market from a low-mix business with a few high-volume commodity products to a higher mix business with a diversity of parts.
This market shift is expected to drive changes in the longstanding test strategies of DRAM manufacturers. Figure 2 shows a high-level model of DRAM test flow, indicating that devices go through at least three test insertions.
At today’s memory densities, most wafers have very low, if any, yield without repair. During the probe test, all of the failing bits of a memory under test must be captured by the test system and analyzed to determine if the die is repairable. This requires a very large memory subsystem known as the Catch RAM to store a bit image of all device test results, and redundancy analyzers, essentially parallel processors, to execute the complex algorithms that determine if a die is repairable. After probe test, the next step is laser repair where spare elements are electrically mapped in to repair the failing bits.
Test Time Per Wafer Dominates Probe Economics
The shift to consumer and communications applications for DRAMs does not reduce cost pressures. Indeed, it may increase them as much of the growth is driven by end products with average selling prices (ASPs) much lower than the PC market. ATE manufacturers will have to be innovative to support a growing diversity of probe requirements while reducing test costs.
The standard economic model for wafer test considers four major factors:
- The time it takes to test a wafer.
- The capital cost of the test cell: test system and probers.
- The cost of probe cards.
- The depreciation periods of the test cell and the probe cards.
Sometimes a fifth factor—the economic life of the test cell—is considered. The time it takes to test a wafer is the dominant factor in the cost of wafer test.
How Much Time Does It Take to Test a Wafer?
Probe cards for wafer test typically use a rectangular array of contacts. The wafer prober lifts the wafer into contact with the probe card. This is referred to as a touchdown of the probe card onto the wafer. The objective is to contact every die and make the fewest possible touchdowns per wafer:
Test Time/Wafer = # Touchdowns × Test Time/Touchdown
The number of touchdowns required to test a wafer typically is limited either by the probe-card contact area or the number of die a particular system can test at one time. Today, this typically would mean 10 to 30 touchdowns at 32 in parallel. With new probe-card technologies able to contact one-quarter of an 8² wafer, the limitation more and more often is the test system.
Proliferating Device Types Break Existing DRAM Probe Architectures
The traditional approach to development of a probe test system has been to add Catch RAM and repair analysis capability to an existing package test system. This leveraged development costs across segments of a cost-sensitive market and, until recently, met the probe requirements of DRAM manufacturers. This model breaks in a world where growth in the DRAM market no longer is driven by high-volume commodity parts.
With package systems, the number of die that can be tested in parallel is fixed. The number of pins on a high-volume DRAM package is set by standards bodies like the JEDEC Solid State Technology Association. In fact, the test system usually is sized to match a particular generation of device handling equipment. There is no reason to impose the design complexity of a flexible architecture on a package test system.
The requirements at probe are rapidly diverging. The number of test-system pins required to probe a DRAM differs dramatically from one manufacturer to the next. Some semiconductor manufacturers test at the full I/O width at probe while others compress I/Os, requiring as few as four to test a standard SDRAM part.
In addition, the availability of large-contact-area probe cards has encouraged some manufacturers to share test-system address/clock and DC measurement pins to further reduce the test-system resources required for each die. This allows two or, in some cases, four die to be tested in parallel in the rigidly defined sites of the package-based probe system.
The current DRAM market trend, with the move to wider I/O communications and consumer parts that are more likely to be shipped as bare die, will mean that more and more DRAM die will be tested at 16 and 32 I/O. It is increasingly probable that every manufacturer will have a range of DRAM designs that require different I/O widths at probe. As a result, a test system with rigidly defined sites may have as many as 40% idle pins for some wafers and be stretched to the limit or forced to cut parallelism in half for others. Figure 3 shows how increased capacity is supported by a test system with flexible site boundaries.
A number of problems must be solved to ensure that the number of touchdowns is minimized for every DRAM wafer—with any test strategy. Here are the challenges ATE manufacturers are dealing with as they search for ways to lower test costs despite the growing diversity of DRAM parts:
- How do the rigid site architectures of DRAM probe systems change to allow optimal use of resources for each new wafer?
- How do you handle the large number of I/Os required to minimize touchdowns since the I/O channels can never be shared?
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How do you eliminate other resource bottlenecks that slow testing, such as Catch RAM capture speed and capacity and parametric measurement resources?
Minimizing the Test Time Per Touchdown
The key to lowest cost at probe is to minimize the number of touchdowns without incurring test-time penalties because of bottleneck resources in the test system. The most significant of these bottlenecks are the fail capture and redundancy capability of the test system. Here’s why:
The size of the required Catch RAM becomes large quickly because it doubles with each device generation and with each doubling of the number of die tested per touchdown. To cope with higher speed devices, the Catch RAM is multiplexed so the amount of RAM increases again.
For example, a 512-Mb device with 8:1 I/O compression occupies 64 Mb in the Catch RAM plus 25% to 50% in the redundant cells. A wafer probe system operating at 125 MHz and providing 128 die per touchdown on two test stations requires from 40 to 50 Gb of Catch RAM for this device.
As the DRAM product mix increases, manufacturers will increasingly discover that the traditional probe test-system architecture no longer offers a cost-effective solution. The diversity of probe requirements demands an architecture that can mix and match resources fluidly, handle standard I/Os one day and wide I/Os the next day, and remove the bottlenecks that slow down the pace of test and drive up costs. ATE manufacturers have their work cut out for them.
Solving the Catch RAM Dilemma
Minimizing test time per wafer in today’s rapidly changing DRAM probe market means that the test-system’s fail capture and analysis capabilities must advance to previously unattainable levels in terms of speed and capacity, configurability, and cost. Teradyne’s new Probe-One Memory Test System uses 1M-gate CMOS ASIC technology and standard PC133 SDRAM DIMMs to provide a Catch RAM that can be expanded to 384 Gb per system while maintaining costs comparable to much smaller SRAM Catch RAMs.
Three primary technological advancements enable the DRAM Catch RAM design. First, a semicustom ASIC was developed to control and arbitrate the fail data flow to the DIMM modules. In addition, the ASIC exploits the large amount of available memory by arbitrating concurrent capture of new data while data from a previous test is being scanned and processed by the 512 PowerPC™ redundancy analysis processors. This creates a dual Catch RAM, enabling manufacturers to analyze failure information on a per-pattern basis without incurring a test delay to transfer data out of the Catch RAM for analysis.
Second, a new power-regulation technology accommodates the current variations typical during access and refresh of large banks of DRAM memory. Local high-bandwidth regulators are used to maintain stable memory supply voltages during surges as high as 70 A.
Finally, a PCB was developed to support a large number of SDRAM DIMMs and the associated 1,088-pin ASICs. A 20-layer, high-component-density design meets the technical requirements while being manufacturable and reliable.
This design places the Catch RAM on the same cost down curves as the market it serves and removes the limitation on capacity. The result is a DRAM probe architecture that supports testing at speeds up to 250 MHz for devices as large as 2 Gb. Other systems, with SRAM Catch RAMs smaller than 10% of the capacity of the 384-Gb DRAM design, must limit the number of die tested per touchdown, the speed, or both when the device requirement exceeds the available Catch RAM.
About the Author
Carol Lemlein is product manager for the Probe-One System in the Memory Test Division at Teradyne. Ms. Lemlein has been at Teradyne for 18 years, holding positions in engineering development and product marketing for digital and memory test systems. She received a bachelor’s degree in physics from Brown University and a master’s in management of technology from the Massachusetts Institute of Technology. Teradyne, Memory Test Division, 30801 Agoura Rd., Agoura Hills, CA 91301-4324, 818-874-7589, e-mail: [email protected].
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July 2001 |