The JEDEC 35 Standard (EIA/JESD35, Procedure for Wafer-Level Testing of Thin Dielectrics) describes voltage ramp (V-ramp) and current ramp (J-ramp) tests to monitor oxide integrity. These tests are meant to provide quick feedback on oxide characteristics, but instrumentation settings can apply the brakes to test speed and obscure soft breakdown visibility.
Device Reliability Testing
In MOSFET and ULSI process design, oxide defects may limit device reliability, especially if the oxide thickness has been scaled to a few atomic layers. The JEDEC 35 Standard defines V-ramp and J-ramp tests that can reveal these defects.
Typically, JEDEC oxide breakdown tests are performed with an automated parametric test system or semiconductor characterization system. The main instruments used in these systems are source-measure units (SMUs), which have a number of features to get the most reliable results in the shortest time possible. Nevertheless, the instruments need to be configured properly for:
- Accurate voltage and current source-measure performance.
- Precise step-time control.
- Automated device parameter extraction.
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Data analysis routines specific to J/V-ramp methodology.
V-Ramp and J-Ramp Test Techniques
The V-ramp test applies a linear voltage ramp; the J-ramp test applies an increasing logarithmic current ramp until oxide breakdown. The V-ramp test begins at a low oxide voltage so it is better at detecting low electric field failures, but it provides poor resolution at high electric fields. The J-ramp test is just the opposite; it starts at a relatively high oxide voltage, so it provides poor low electric field resolution but better resolution at high electric fields.
This resolution difference has led to the V-ramp test often being used to determine infant mortality and low electric field fallout on larger test structures, such as extrinsic failures. The J-ramp test often is used on smaller test structures where the oxide failure mode is expected to be intrinsic.
Figure 1 illustrates the V-ramp test procedure. The sequence begins with a pre-test to determine initial oxide integrity. During pre-test, a constant voltage (Vuse) is applied to a test structure (DUT) and the oxide leakage current measured. If the oxide is determined to be good, then a linear voltage ramp is applied to the DUT until oxide failure occurs.
Oxide failure is easy to spot because of the sudden increase in current, which is about 10 times the expected value, or from a measured oxide current that exceeds the specified compliance value. A post-test, also performed at Vuse, determines the final state of the DUT. Parameters extracted from V-ramp measurements include the breakdown voltage (VBD) and the charge to breakdown (QBD).
The J-ramp test methodology is similar to V-ramp, beginning with a pre-test of oxide integrity. In this pre-test, a constant current (typically 1 µA) is applied and the voltage across the oxide measured. If the DUT is good, an increasing logarithmic step current [given by Istress = Iprev * F, (where F < 3.2)] is applied until oxide failure.
Oxide failure is detected when the voltage across the oxide drops 15% or more from the previous measured voltage (Vprev) or the predefined charge limit is exceeded. A constant-current post-test assesses the final state of the DUT. Extracted J-ramp oxide breakdown parameters include VBD and QBD.
Test Difficulties
This all sounds simple enough, but measurement difficulties can be encountered with either test procedure. The voltage or current step time must be as uniform and precise as possible to determine VBD and QBD accurately. In practice, it may be difficult to precisely control the step time of a voltage or current source from an external PC because of resolution and accuracy limitations associated with the PC’s internal clock. Also, instrument effects such as range changes can create unpredictable step-time variations.
Instrument manufacturers have developed various ways of dealing with timing uncertainties. One design uses an integral PC-on-a-board tightly integrated with the SMUs, all of which are installed in a PCI backplane. The PC provides configuration control of the instruments, which can be programmed for fixed voltage source and current measurement ranges, eliminating autoranging and its effect on voltage step time.
In a V-ramp test, the gate source SMU is set for a linear voltage sweep from 1.8 V to 6.0 V and a voltage step of 0.035 V. This voltage step size is based on the assumption of a 3.5-nm thick oxide and application of the JEDEC 35 Standard’s 0.1-MV/cm maximum voltage step height.
Measurement timing must be precisely controlled, which is done by setting an appropriate sweep delay for each voltage step before a measurement is taken. Rather than using default instrument settings, customized adjustments are made to the measurement integration time, sweep delay, and hold time to get the best results.
For example, the source’s linear voltage ramp sweep settings can be programmed for an A/D integration period of one power line cycle (PLC), which for 60 Hz is 1/60 s or 16.6 ms. Then a sweep delay of 83 ms is added to this to create a step time of »100 ms (83 + 16.6), yielding a voltage ramp rate of 1 MV/cm-s in accordance with the JEDEC 35 Standard. Programming a voltage hold time of 0.2 s for the first voltage step is enough to allow for displacement current settling before the voltage sweep begins.
With these settings, results should be similar to those shown in Figure 2. The text box inside the graph lists voltage and current at breakdown along with other parameters. This data could be read from numerical data pairs or from an Ig – Vg plot.
When determining QBD, step timing must be precise, so it should be verified before using test results. An instrument time-stamp feature that saves precise timing information for each voltage step facilitates this verification. Post-test analysis of timing data showed that the voltage step time averaged 99.5 ms (expected value 99.6 ms) with a standard deviation of ±0.062 ms.
A more subtle measurement problem may occur as oxide is scaled thinner than 3 nm. At about this thickness, a new and important phenomenon begins to appear in the oxide—soft breakdown.
In thicker oxides, the effects of a breakdown typically are catastrophic, such as irreversible damage. In ultra-thin oxides, the breakdown may be less dramatic. When soft breakdown occurs, a large increase in current won’t be seen as would be in a thick oxide breakdown. Often, after a soft breakdown, the oxide still may exhibit some insulating properties, even though they are significantly degraded.
Soft breakdown poses additional challenges in V-ramp and J-ramp testing. Since the breakdown is less dramatic, detecting it is more difficult.
There are several techniques for detecting soft breakdown, the most common one being observation of the breakdown current noise. A sudden increase in the noise level indicates a breakdown.
To make this determination, the current measurement instrument must be programmed for the shortest integration time possible, so that it does not average out the noise in the measurement. Longer integration periods are designed to eliminate noise errors and tend to obscure sudden noise increases. With a short integration period and appropriate test algorithm running on the PC controller, the measurement results can be used to calculate current noise.
For this reason, the key factor in detecting current noise is the capability of an SMU to make fast low-level measurements. If the instrument relies heavily on filtering and signal integration to make sensitive measurements, this not only limits the ability to detect an increase in noise such as soft breakdown, but also reduces measurement speed and throughput.
V-Ramp Data Analysis
Commonly, the parameters analyzed in a V-ramp test include the breakdown current (IBD), VBD, QBD, and time to breakdown (TBD). Basic sweep data will clearly identify a sudden increase in current at breakdown, but the other parameters must be extracted from the V-ramp data set (Figure 2).
Various instruments have different ways of extracting these parameters with built-in analysis functions. A typical method uses math functions that operate on collected data that has been stored in a spreadsheet format. Once extracted, parameters can be displayed automatically by using the instrument’s graphing functions, which may be an extension of spreadsheet capabilities.
J-Ramp Test and Data Analysis
Whatever instrument is used, its J-ramp and V-ramp test setups will be similar. The gate source SMU is programmed to perform a logarithmic current sweep from 10 nA to 0.6 mA, where the number of steps in the current sweep is 50 (F = 1.25).
A fixed-voltage measurement range will minimize the effects of autoranging on step time. As with the V-ramp test, the SMU step time must be precisely controlled. The JEDEC 35 Standard specifies a current ramp rate of one decade/500 ms.
Again, the instrument’s math and spreadsheet functions are used to extract J-ramp oxide breakdown parameters. The J-ramp oxide breakdown characteristic curve is shown in Figure 3.
Oxide Defect and Ultra-Thin Oxide Characterization
Oxide defects can create excessive tunneling currents at low electric fields. In addition, ultra-thin oxides (<6 nm) show substantial direct tunneling oxide currents at low electric fields. To study these effects, the instrumentation must be sensitive enough to allow monitoring of oxide currents in the femtoamp range. Figure 4 shows the results of an Ig – Vg sweep on a 3.5-nm oxide generated by an instrument with a noise floor sufficiently low (~10-15 A) to reveal tunneling current at the low end of the sweep.Generally, finding design and processing flaws early on helps shorten development cycles and time-to-market. As a result, in addition to high throughput of precision J-ramp and V-ramp measurements, the semiconductor characterization system should include software that allows easy test development, preferably without the need to write program code.
This is especially important if the system is shared with occasional users who are not accustomed to programming. Furthermore, the test instruments and hardware interfaces in the system should facilitate integration with all other sourcing, measuring, and switching systems needed for today’s wide range of semiconductor test requirements, such as capacitance-voltage (C-V) measurements.
Additional Electrical Characterization Techniques
V-ramp and J-ramp tests are very popular because of their simplicity and throughput advantages. But, the main drawback is their empirical nature: it is difficult to identify the underlying cause of oxide breakdown with them. Other analytical and electrical techniques may be needed to determine the defects that lead to oxide breakdown.
One of the most common electrical techniques is C-V characterization. C-V measurements can be used to study oxide and oxide-silicon interface properties down to about 1-nm thickness.
About the Authors
Douglas Brisbin currently is employed by National Semiconductor where he is involved with device testing and characterization. Previously, he was lead applications engineer in the Semiconductor Business Unit at Keithley Instruments.
Qi Wang has served as lead applications engineer and currently is involved in product marketing at Keithley Instruments. Dr. Wang has more than 15 years experience in semiconductors, optical physics, and DC and RF measurements.
He received a Ph.D. in physics from Texas A&M University and a B.S. in physics from Beijing Normal University. Keithley Instruments, 28775 Aurora Rd., Cleveland, OH 44139, 440-248-0400, e-mail: [email protected]
For More Information
Application Note on C-V Characterization
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August 2002