From the application point of view, one of the most significant parameters for the DDR SDRAM device or module is the time duration over which valid data can be read from the memory. This parameter is termed tDV.
|ATE||automatic test equipment|
|CAS||column address strobe|
|Clk/Clk#||differential input clock where Clk# is the invert of Clk|
|DDR||double data rate|
|DQS||write/read data strobe|
|DRAM||dynamic random access memory|
|EDO||extended data output|
|Mb/s||million bits per second per pin|
|SDR||single data rate|
|SDRAM||synchronous dynamic random access memory|
|T||data rate in ns|
|tAC||data access time from Clk/Clk#|
|tDQSQ||data strobe edge to output data edge skew time|
|tDQSCK||DQS output access time from Clk/Clk#|
|tDV||data valid window; time window per output byte when data is valid to read|
|tHP||minimum clock low/high time|
|tOH||output data hold time|
There are many parameters, both electrical and physical, that contribute to the relative size of tDV and not all scale with operating speed. Factors such as signal noise, crosstalk, skew, jitter, and drift effects brought on by voltage and thermal variations contribute to the reduction in the tDV. These variations impact testing tDV for wide data path DDR-I SDRAM and higher data rate DDR-II SDRAM devices.
The mid 1990s saw the development of SDRAM memory technology allowing faster data access than the EDO DRAM in common use at that time. SDR SDRAM memories use a synchronous interface with all inputs referenced to the rising edge of an incoming clock. Initial operating speeds were set at 66 MHz (PC66), where data could be output and input in 15-ns intervals. In keeping with Moore’s Law, the next 18 to 24 months produced a doubling of the basic speeds to 7.5 ns (PC133) with a small number of manufacturers producing PC150 and PC166 devices.
In the late 1990s, the memory industry saw another paradigm shift to even higher data rates. This was the genesis of the current DDR SDRAM device design and manufacturing efforts.
DDR SDRAM data is sampled relative to both edges of the input clock, doubling the effective data rate/bandwidth of the memory over SDR SDRAM devices. The data rate for mainstream production DDR SDRAM today is expected to be the PC266 (133-MHz clock) where the device receives or sources data every 3.75 ns.
With the ever-increasing speed of memory devices and modules, manufacturers of memory test equipment have had to keep pace with the expectations of their customers. With the advent of DDR devices and modules, however, testing has become significantly more difficult.
Defining the tDV Parameter
Before we discuss tDV testing in DDR SDRAM, let us first consider the operation of SDR SDRAM. Figure 1 depicts a typical timing diagram for a read cycle associated with SDR SDRAM devices.
After the read command, the output data is valid n clock cycles later, depending on the CAS latency being used. All output data becomes valid at tAC after the rising edge of the clock signal, typically 5.4 ns for a 133-MHz device. The output data remains valid until at least tOH after the next rising edge of the clock or typically 2.7 ns. So the minimum tDV for an SDR SDRAM device is (T – tAC) + tOH.
If typical values are inserted for a PC133 device, then:
tDV (minimum) = 7.5 – 5.4 + 2.7 = 4.8 ns
This tDV value is large enough to easily place a result strobe, even with low-cost test equipment that has an edge-placement accuracy of ~1 ns.
With DDR SDRAM, a typical read cycle has some commonality with SDR SDRAM as well as some significant differences:
- The clock is implemented as ClkClk# to the memory.
- The device drives DQ on both edges of the clock, twice the rate of SDR SDRAM.
- An additional bidirectional DQS is used.
During a read cycle, the DQS output is driven by the memory being accessed and is edge aligned with the output data. Each transition of the DQS signal is accurately positioned at the front end of its associated data output. When routed properly to the circuitry receiving the data, this signal provides a precise marker indicating the existence of valid data. On wide data path devices, there is a DQS signal per data byte.
Figure 2shows the tDV of an 8-b device using the AC characteristics of a typical DDR SDRAM memory. For read operations, the DQS signal toggles at the same time as the output data transition for each new piece of data. Ideally, the DQS transition occurs in the center of the spread of transitions of the associated DQ signals.
From Figure 2, the key timing parameters are the following:
- tDQSQ: DQS to DQ skew, DQS to last DQ valid, per group, per access; typically 0.50 ns for a PC266 device.
- tOH: DQS to DQ hold, DQS to first DQ to go invalid, per access; typically tHP is 0.75 ns for a PC266 device.
The tDV for a single device is approximated as tOH – tDQSQ.
Table 1 computes tDV for a DDR-I SDRAM operating at 7.5 ns (266 Mb/s) and DDR-II SDRAM devices operating at 5 ns (400 Mb/s) and 3.75 ns (533 Mb/s).
The Vanishing tDV
With the basics of the SDRAM parameter tDV defined, we now can show why this parameter concerns both memory manufacturers and system designers. As shown in Table 1, the tDV is shrinking as we move from SDR SDRAM to DDR-I and DDR-II SDRAM memories. Obviously, tDV must reduce as the operating speed increases, but in fact, the tDV reduction is greater than the overall 2:1 speed increase.
The issue of an ever-decreasing tDV is further magnified when these devices widen to have 16-b or 32-b data buses. Besides the traditional issue of dv/dt and di/dt for wider devices, there is an added dimension because the memory design sports multiple DQS pins: one per output data byte.
The effects from internal and external sources conspire to shift the DQS and related DQ outputs in a random manner. However, the timing of each output byte and its associated DQS signal is independent of the other outputs. It’s only when all 16 or 32 data outputs are thought of as having a single tDV applied that the impractically tight timing results appear.
There is a parameter intended to account for internal effects: tDQSCK. This is a jitter and skew specification between the incoming clock and the outgoing, on-chip-generated data strobe signal. The effect of tDQSCK is shown inFigure 3.
In Figure 3, the tDV for each byte of the device output is depicted by the signals DQ (0-7) and DQ (8-15). Transitions on each DQS signal for the chip must fall within the window defined by the parameter tDQSCK. This parameter determines the limits of the access window for DQS from Clk/Clk#, that is, DQS jitter. If the data and DQS from the two bytes output by the device are skewed + and – by the maximum value of tDQSCK, then:
Full Chip tDV = tDV for the byte – (2 × tDQSCK)
Table 2shows this calculation for the DDR-I at 266 Mb/s and the DDR-II devices at 400 Mb/s and 533 Mb/s.
When performing a read operation, the accurate positioning of the result strobe within the tDV is essential. Modern memory test equipment supports result-strobe placement with respect to the clock edges that it generates as input to the device being tested. Clearly, what’s needed is the capability to position separate result strobes relative to each output byte’s DQS signal.
Even today’s moderately priced test equipment struggles to reliably position a result strobe with greater than ±400-ps accuracy. Based on Table 2, using all but the most expensive of test equipment to evaluate tDV in DDR SDRAM memories is a recipe for failing good devices and reducing test yields.
This is further complicated by the effects of the skew and jitter of the clock signals from the tester plus the varying track lengths associated with these signals that can cause an impedance mismatch. Both of these critical factors can reduce the tDV by as much as ±0.5 ns, leaving it at almost 0, if not a negative value.
Table 2 also shows the effect on tDV as device and test speeds increase. The tDV will continue to decrease at an alarming rate. For example, tDV for a byte-wide PC400 DDR SDRAM is expected to be approx-imately 1.6 ns; a PC533 memory will see tDV at approximately 1.1 ns. However, a ×16 or a ×32 PC400 DDR device is expected to have tDV values of approximately 0.65 ns while a PC533 DDR memory can exhibit tDV values in the range of 0.3 ns. These values are at or below the base accuracy of all but the high-cost test systems available today. As a result, we have the concept of the vanishing tDV.
Testing for tDV
No doubt the tDV for a multiple byte-wide DDR SDRAM is an important parameter of the device, and it must be tested. Rather than buying expensive high-precision test equipment, why not use the multiple DQS signals from the chip, one per byte of the output data?
Understanding that the chip design is aimed at keeping each DQS and its related data byte grouped together, then it is better to test them together. For each byte of data and its related DQS, perform the normal tests.
Figure 3 plus Tables 1 and 2 show that the required tester accuracy to test this tDV is much lower than trying to do a chip-wide tDV test. On an engineering tester, there usually are tools to create graphical representations of these values using shmoo-plot procedures and graphical outputs. Production test equipment also can compute an overall tDV but will avoid graphical displays to maintain essential throughput. This testing approach is fully applicable to DRAM memory module test.
Another possibility has the testers using the DQS signal as a trigger for the result strobe with new hardware. This method would trigger the result strobe on each byte of the data using the related DQS signal since the DQS strobe is meant to signify the validity of the output data for its related DQ byte, reducing the effects of tDQSCK and tDQSQ on the parameter tDV. In this manner, the challenges of testing tDV would be significantly reduced.
This approach is equally applicable to DRAM memory module test. For example, a 72 I/O module with up to 18 chips provides one DQS per chip, and those signals could trigger the result strobe for the data coming from each chip. Similar savings in terms of testing tDV could be realized here, just as it would be for device test.
As memory technology continues to evolve, extending the limits of speed, density, and tolerance variations, two challenges manifest themselves:
- Memory manufacturers cannot afford to purchase or replace multiple million-dollar testers to address advancing production or engineering test needs.
- Memory ATE vendors are tasked with the challenge of designing affordable solutions with protection against long-term obsolescence. These problems are exacerbated by the volatility of eroding memory margins and ever increasing device complexity.
Testing to match the application allows device manufacturers and users to reduce the pressure on their test equipment to measure such high tolerances and shrinking parameters. Modern memory designers and manufacturers must seek no-compromise solutions today. These must embody flexibility, affordability, performance, and production throughput as well as value-added tools to address engineering needs. This kind of application-aware testing, coupled with a proper and complete effort in design for testability in new designs matched by ATE with the required test tools, is the stepping stone to a more affordable and more complete testing future.
About the Author
Brad Snoulten is the director of advanced product marketing at MOSAID Systems. He has more than 20 years experience as a test and product engineer, a memory test applications engineer, an application manager, and a test-system architect. Mr. Snoulten holds a BaSc in electrical engineering from the University of Waterloo and a Diploma in Electrical Technology from Ryerson Polytechnic University. MOSAID Systems, 3375 Scott Blvd., Suite 206, Santa Clara, CA 95054 613-599-9539, e-mail: [email protected]
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