A Test Solution for Embedded Reprogrammable Cores

Two companies have joined forces to optimize quality, integrity, post-programming validation, and cost for embedded test of reprogrammable logic cores.

The increasing complexity of system-on-a-chip (SOC) designs creates significant challenges in testing the functional modules of the completed silicon. With the increasing development and use of intellectual property (IP) cores that once prospered as discrete components, the traditional testing approach has become, at best, time consuming and, at worst, ineffective. Problems of efficiently and effectively testing modules inaccessible from the pins still remain a paramount concern.

Embedded RAMs, embedded microprocessors, and embedded logic functional cores all present opportunities to structurally test a fixed architecture delivering a fixed function. New on the scene are reprogrammable logic cores, which present a completely new set of considerations for embedded test. Their architecture and core size are fixed but, by design, the logic function being implemented is permanently flexible. These aspects create the opportunity to build a test solution for embedded, reconfigurable cores using a number of methods.

As an example, we will show how LogicVision and Actel worked together to develop a built-in self-test (BIST) solution for reprogrammable embedded logic cores. We will examine Actel’s embedded field-programmable gate array (FPGA) EPGATM Embedded Programmable Gate Array VariCoreTM IP and describe an effective test approach.

Testing IP-Based Designs

IP or core-based designs pose unique test challenges due to the added complexity of dealing with the integration of several diverse functional blocks. Test techniques have been developed to deal with many blocks including embedded memory, random logic, and certain analog blocks.

With the emergence of configurable and reconfigurable embedded functions, additional test challenges exist. Core-based design tests often are addressed using a divide-and-conquer approach where access and isolation become key aspects to the solution. To address the complexity, associated test times, and external ATE requirements, embedded test often is used.

By combining embedded test techniques along with access and isolation mechanisms, a fully scalable hierarchical test solution emerges. The reconfigurable blocks also can be handled with this same common test methodology.

Reconfigurable Logic Test Challenges

Reconfigurable logic blocks provide the capability to change their underlying function over the life of the host SOC. During device verification and through the manufacturing phase, the embedded logic function may not be fully defined and committed.

Traditional functional test requires the programmable logic to be defined in addition to a potentially lengthy initialization phase prior to applying test patterns. These facts favor a structural test approach for both the embedded array and the rest of the SOC.

Reconfigurable logic blocks commonly are built from a regular array of routing resources and programmable logic functions. Similar to component FPGA devices, embedded reconfigurable logic must be tested at manufacturing to ensure that the block is defect free and can accept any valid user configuration.

A distinction often is made between structural-array testing and end-user logic testing. For manufacturing purposes, it is important to verify the complete array. For end-user logic testing, the concern is with a particular function. By using embedded test, both aspects can be covered with a single solution.

Actel’s VariCore EPGA IP block, a reprogrammable SRAM-based core, contains fixed architecture structures and interfaces to facilitate test. A BIST interface can be connected directly to a LogicVision embedded test-controller IP block. This test controller provides autonomous self-test of the array.

Figure 1 illustrates the VariCore architecture along with its dedicated test controller. The embedded test controller can be provided by Actel, or the SOC integrator can easily generate the controller using the files and scripts provided.

The array with the embedded test controller then becomes similar to any other block with embedded test that is being integrated into the SOC. The test control interface conforms to either an industry-standard interface such as IEEE P1500 or the LogicVision proprietary core test interface.

Test Specifics

VariCore EPGA IP blocks are reprogrammable, soft-hardware, embedded IP cores. The VariCore reprogrammable EPGA core contains a core-specific BIST interface, which allows an external BIST controller to gain access to the scan chains within the VariCore EPGA IP block. These scan chains allow all of the user registers and I/O locations within the core to be loaded and sampled by the BIST controller.

There is no need for the designer to insert scan chains within the EPGA logic function; the scan chains implemented under the EPGA logic core are reused. The number of scan chains varies depending on the core size; a typical array has 16 internal and eight boundary scan chains.

The BIST interface allows for external and internal test of the core. Through the BIST interface, the external test controllers can capture and drive all the I/O terminals, allowing interconnect to surrounding blocks within the SOC device to be tested independently of the function implemented in the EPGA.

The internal function also can be tested using ATPG or logic BIST technologies. At the BIST interface, the user design is a single, full scan, multiplexed, flip-flop circuit.

Functional Implementation

During initial design creation, the EPGA function is coded using standard design capture methods in the same manner as the rest of the SOC. Complete system functional verification can be performed ignoring the actual physical implementation.

During implementation, the IP blocks are synthesized and compiled targeting the VariCore device. The compile stage generates a bit stream for programming the device along with various netlist views used for verification.

The basic view is a simple netlist that implements the user function. The next view includes models of the configuration, JTAG, and BIST interfaces.

Finally, a view that replaces all the user’s registers with underlying scan chains is generated. This is used by LogicVision’s LogicBIST software tool to verify that the design meets LogicBIST design rules and creates the expected signatures for the implemented user function.

Figure 1 shows the VariCore block in the context of an SOC design. The top-level integration of the IEEE 1149.1 test access port (TAP) and boundary scan completes the hierarchically testable design. The TAP serves as an embedded test manager and is used to initiate tests and record results. The TAP within the VariCore block can be accessed by sharing top-level TAP pins or through daisy chaining with the top-level TAP.

Manufacturing Test

Manufacturing test of the SOC consists of internal tests of individual IP blocks and the top-level test of interconnect between blocks including any glue logic. The VariCore I/O interface coupled with the LogicVision test controller allows the top-level test to be generated using either ATPG scan or logic BIST and is independent of internal logic within the array.

Embedded test commonly is used for the internal tests of each IP block. For the VariCore block, the internal tests consist of a combination of applied external patterns and self-test. The external patterns commonly are applied serially through the JTAG interface. It is anticipated that self-test eventually will provide the majority of coverage to overcome the serial nature of the externally applied patterns.

The manufacturing test addresses the following:

  • Configuration memory.
  • Routing track.
  • Routing switch.
  • Logic module.
  • Memory block.
  • User-logic self-test if required.

Manufacturing diagnostics and root-cause analysis also are included as part of the hierarchical test solution.

End-User Test

A particular logic configuration can be validated for both functionality and performance by initiating a logic self-test. As part of its design flow, Actel provides a netlist view compatible with LogicVision’s analysis tools that allow coverage assessment as well as expected signature generation. For repeatable signatures, the user logic must comply with a set of design rules.

These design rules typically are similar to rules for all logic. Random-pattern testability is not an issue since the architecture inherently has a high register content and unused logic can be used to improve controllability and observability.

In-field validation is becoming more of a concern with the inclusion of reconfigurable logic on complex SOC components. Not only must the fixed logic be tested for parametric and structural defects, but the programmable logic also must be tested. The successful completion of the programmable logic self-test validates both the logic structure and the secure transport of the programming bit stream. Errors in these bit streams caused by programming mistakes or by using an incompatible version of software are easily detected.

Conclusion

Reprogrammable embedded logic cores have emerged to combat the rising costs associated with leading-edge application-specific integrated circuit (ASIC) and application-specific standard product (ASSP) designs. A hard IP SOC design flow combined with a standard FPGA design flow is necessary to complete the logical and physical verification.

Inherent SOC test complexity is exacerbated with the inclusion of reprogrammable logic cores. Embedded test and a hierarchical test methodology become the only viable approach.

About the Authors

Ian Bryant is the methodology and technical marketing manager for embedded FPGA at Actel. He joined the company in 1996 as an HLD consultant in the United Kingdom and transferred to the United States in 1999. Mr. Bryant, who has a BSc Hons in computer and microprocessor engineering from Essex University, previously held applications positions with Synopsys and was involved with ASIC design with several European networking and defense contractors. email: [email protected]

Dwayne Burek joined LogicVision in 1994 and today is the company’s chief technical director. He received an M.S. in electrical engineering from the University of Manitoba and, after graduation, joined Bell-Northern Research (now Nortel Networks) as a member of the scientific staff. LogicVision, 101 Metro Dr., San Jose, CA 95110, 408-453-0146, email: [email protected]

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Published by EE-Evaluation Engineering
All contents © 2002 Nelson Publishing Inc.
No reprint, distribution, or reuse in any medium is permitted
without the express written consent of the publisher.

December 2002

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