Convergent SOCs Challenge Mixed-Signal Test

As the consumer market for voice, audio, video, and data services evolves, the SOC test platform must unite a variety of leading-edge test capabilities.

After talking about it for years, convergence in consumer electronics is one of the biggest trends in the high-tech world today. Voice, audio, video, and data services are coming together in a wide range of consumer applications, such as 2.5G/3G handsets and next-generation residential gateway and digital set-top boxes.

In mobile applications, 3G cellular with its high data rates will be able to support data (e-mail and Web surfing), location, video, and audio services in addition to current voice services. Similarly, within the home or home office, it is not unusual to find cable, satellite, or terrestrial video, audio, and data coming into the residence along with CD, DVD, and MPEG content from a variety of sources, including digital still and video cameras (Figure 1). With all this information cascading into and through the home, the set-top box seems the most likely candidate to manage the content and distribute it throughout the home.

One of the key enablers of this convergent trend in the home, home office, and mobile appliances is the mixed-signal system-on-a-chip (SOC). However, this does create some interesting challenges for test, specifically for IC test. These broadband devices are being shaped by higher integration levels, increased performance driven by higher data rates and new multimedia applications, and most importantly, cost pressures. That is why it is imperative to keep the cost of test under control without sacrificing the quality of test.

Complex Mixed-Signal ICs

To save on development costs, several SOC vendors today are creating ICs that include a wide range of computational, communications, and entertainment functionality. The devices require all these capabilities because their job is to obtain content from a variety of communications methods and protocols, decode that content, and then display, distribute, or store the content.

Although these SOCs will be used in a variety of applications such as digital set-top boxes, cellular handsets, and advanced personal digital assistants (PDAs), it should come as no surprise that they share remarkably similar architectures: they all include the capability to encode/decode and then display, distribute, and store convergent voice, video, audio, and data. To that end, these SOCs contain an assortment of intellectual-property (IP) blocks including logic cores, memories, embedded processors, and a range of mixed-signal and RF cores.

Any or all of these IP blocks could be integrated on the SOC. For example, the typical digital set-top box architecture can be divided into three functions: channel decode (tuner/demodulation/forward error correction [FEC]), source decode (demux and decode the content MPEG, audio, VoIP, JPEG, and data), and distribution to the display, speakers, PDA, PC, or storage medium (Figure 2).

To drive down the manufacturing cost of these set-top boxes, the trend is toward capturing their functionality on fewer chips. One possible architecture is a front-end chip that integrates the tuner and analog-to-digital converter (ADC)/demodulator and a back-end IC that supports MPEG, graphics, the core processors, peripherals, and buses.

Challenging IC Testing Requirements

Given that these SOCs are highly elastic in the capabilities they provide, the exact test requirements are a function of the integrated IPs, the test strategies defined by the engineering staff, and cost-of-test pressures. But there is no doubt that these SOCs will require the full gamut of testing capabilities from RF and mixed-signal to high-speed digital, memory, and scan test.

To test the various IP blocks using traditional ATE requires multiple insertions using multiple-point solution testers. Obviously, this is not a cost-effective approach for these devices.

To keep test cost under control, the optimal solution uses one test platform that provides the full range of test resources. Creating and maintaining one test program for a single platform are much less expensive than dealing with multiple test programs and platforms.

Moreover, the use of one tester offers the opportunity to test IP blocks in parallel, opening the way for higher levels of concurrent test. In fact, IP test blocks probably will become part of the package when the IP blocks are bought and sold.

A true SOC tester requires high flexibility: It must meet mixed-signal requirements, scan vector depths and speeds, and channel speeds to test the range of digital I/O clock and data rates now being integrated on-chip. Advanced analog and RF performance and embedded memory test capabilities also are required.

With pin-counts hitting 450 pins and speeds up to 800 Mb/s on FireWire (IEEE 1394) and 1.65 Gb/s on the digital video interface (DVI) ports, the tester must generate and capture the high-speed digital signals while testing sub-100-Mb/s digital I/O cost-effectively. And as future SOCs aggregate more functionality onto a single piece of silicon, the platform will need to provide a path to accommodate new requirements and scale its pin-count to keep up with ever-larger physical devices. The challenge for the test vendors is to offer an architecture that is advanced yet flexible and keep ahead of the performance and cost-of-test demands these new devices will need.

Testing a Set-Top Box SOC

With all that in mind, let’s take a closer look at the detailed IC test requirements for these consumer ICs. Since the architectures for these devices are very similar, the focus is on a representative chip set for a digital set-top box intended to function as a residential server.

On the front end, the set-top box receives its primary audio and video content from satellite, terrestrial, or cable. Each medium operates under different transmission methods using different bandwidths.

For example, a satellite relies on quadrature phase shift keying (QPSK) and 8 phase shift keying (8PSK) transmission methods with a bandwidth of approximately 30 MHz. Cable supports a more complex transmission method of 64 quadrature amplitude modulation (QAM) or 256 QAM transmission with the bandwidth around 6 MHz. Terrestrial also has a bandwidth around 6 MHz with the most efficient transmission method being orthogonal frequency division multiplexing (OFDM).

Although these three transmission medium schemes are quite different, the underlying decoding architecture is very similar for all three. First there is the tuner portion of the circuitry that captures the incoming signals and tunes them to a specific channel, then the ADC converts the incoming analog signal into a digital signal demodulation.

The FEC takes place before going off chip to the back-end source decoder. The source decoder demuxes the content, which can be video, audio or data, and routes it to the appropriate decode block.

After the signal is processed, it is ready to be encoded back into a digital or analog video or audio signal that the human eye or ear can understand. Additionally, the content may need to be routed to another resource such as a PC, printer, display, or PDA that is connected via point-to-point (USB, FireWire, or Bluetooth).

Now for the test requirements. The front-end tuner requires a set of RF tests to assess gain and compression in the amplifier, harmonic, and intermodulation distortions created from multiple frequencies and gain and phase imbalance. For a satellite set-top box, the RF input signal is 950 MHz to 2.1 GHz. The input RF signal is directly down-converted into a baseband I/Q signal and into an intermediate frequency of 30 MHz with modulation format of QPSK or 8PSK. Although the 30-MHz baseband frequency seems modest, it has 6-b or 8-b resolution.

On the other hand, the cable set-top box has two input signals: one is the in-band channel for the TV signal, and the other is the out-of-band channel used for closed-caption programming information as well as cable-modem data from the front end. The most complex modulation formats are QPSK and 16 QAM that require up to a 10-b ADC.

A 500-MHz, 12-b arbitrary waveform generator (Arb) is required to test these RF signals. The most advantageous arrangement has the Arb fully integrated into the test head on the tester to ensure the purity of the input signals and simplify the fixturing.

As for testing the cable’s return-signal digital-to-analog converter (DAC) that sends user information back to the provider, a 1-GHz, 12-b digitizer fully integrated into the test head is needed to digitize the analog output signal so that the tester can analyze it using digital signal processing (DSP) FFT analysis techniques.

On the back-end portion of the SOC, a new host of testing requirements now comes into play. First are the video and audio DACs for the TV. A 1-GHz, 12-b digitizer needs to be used for the video and a 2-MHz, 16-b digitizer for the high-resolution audio. High-definition TV (HDTV) requires 16 b or even 18 b of resolution for audio. For these measurements, the tester needs a remarkably low noise floor, which can only be achieved if the tester architecture is designed to minimize noise, distortion, and crosstalk.

To save valuable test time, an effective strategy is the one-pass image functional test that verifies all the blocks from the demultiplexer to the video data in a single pass (Figure 3). This test combines elements of digital scan testing with DSP operations to evaluate the resulting video spectrum. Other blocks can be included in this test, depending on the customer’s test strategy.

The input data is the streaming data on the transmission stream (TS) data pin, which contains the real image data, and the output data is the encoded video data. To enable this test methodology, the test platform must supply memory on the order of 100 M of vector memory to make image functional test possible in a single pass.

To provide even multiples of that level of memory for future needs, a good solution relies on test-cycle compression modes to realize more effective memory depth using all the edges supplied by the tester. This methodology used on testing some MPEG back-end devices today has resulted in up to 90% test-time reductions for those IP blocks.

A platform that enables concurrent test of various IP blocks is another characteristic being used to drive down the cost of test for these devices. However, this type of testing has many requirements for both the tester and the device to have independent access and isolation to each core that will be tested concurrently.

Concurrent test requires some thought during the IC design phase to support:

  • Core isolation.
  • Core test access.
  • Interconnect access between cores.

Similarly, on the testing side, consider the architecture of the concurrent test solution. Independent control, processing, timing, and levels of digital and analog resources are required.

For example, the Agilent 93000 SOC solution allows tester hardware to be assigned to the IP cores as ports. The appropriate digital I/O, clock and analog stimulus, and measure resources can be assigned to a specific port. Once this is done, the port is flexible to move around in the test flow either serially or in parallel. Then, based on how well these IP blocks have been isolated at the IC design level, port testing assignments can be made in parallel, as much as the design allows, to achieve the best test time.

Flexibility for Today and Tomorrow

Besides supplying a comprehensive range of test resources, an SOC tester needs to provide true port scalability. Port scalability enables the test engineer to place fast digital pins where they are needed and deep memory where required while populating the remaining pins with lower speed/memory resources to help achieve more cost-effective test. Having the flexibility to place critical capabilities where they are needed ensures the most efficient use of available tester resources.

The mixed-signal source and measure resources in an SOC tester usually are much more expensive than digital resources. However, today’s cost-of-test pressures are leading to SOC testers with multiple channels or cores per resource. Not only does this cut the capital expenditure costs due to less resources purchased, but it also facilitates concurrent test and testing multiple devices in parallel.

The synchronization between the mixed-signal and digital resources must be precise and stable. Some tests, such as the IQ tests on a baseband processor, are checking for phase mismatches between two channels. Any variations on the SOC tester synchronization would cause a test like this to fail, resulting in either failing a good part (lower yield) or retesting of the part (lower overall throughput).

Looking into the future as the consumer market evolves and matures, the test platform also will need flexibility to keep pace. In other words, the test platform must have leading-edge capabilities for a wide range of SOC testing requirements.

Essentially, a convergence of test platforms needs to occur, with a single SOC platform offering combined test capabilities. Such a test platform would provide the flexibility and capabilities needed to successfully address SOC device testing from a technical standpoint and a cost-of-test perspective.

As this market becomes more established, new requirements will undoubtedly emerge, and the SOC capabilities will grow to accommodate those needs. So too, the test platform will need to evolve. If the SOC test platform can easily extend to support these new requirements—more analog and RF, higher speed analog and digital, and increased pin-counts—it will prove much more cost-effective than migrating to a completely new platform or multiple platforms to keep up with the evolution of these devices.

About the Authors

Tom Vana is the worldwide market development manager for SOC test systems for the digital consumer integrated circuit segment at Agilent Technologies. In more than 18 years at the company, Mr. Vana also has held positions in field applications, market development, and product management for the electronics functional test market. e-mail: [email protected]

Don Blair is a principal consultant for Agilent Technologies. He has more than 20 years experience in the mixed-signal test industry, testing audio codecs, video and audio ADCs/DACs, Mil-Aerospace DOD parts, modems, Ethernet transceivers and repeaters, DVD, STB, ADSL, and baseband processors. e-mail: [email protected]

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Published by EE-Evaluation Engineering
All contents © 2003 Nelson Publishing Inc.
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without the express written consent of the publisher.

January 2003


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