Not every die-inspection problem succumbs to emission microscopy. But more of today’s backside challenges are disappearing as CAD navigation software and the microscope join forces.
Emission microscopy (EM) is a key resource for localizing IC defects caused by front-end-of-line problems. Flip-chip packages and chips with many metal layers, which can obscure emissions, do not allow analyses from the active side of devices and need the detection of fault-induced emissions through the backside silicon after package milling and die thinning. Correlating the emissions to physical coordinates in the device layout and elements in the netlist and schematic can be tedious when failure analyses must be conducted from the backside of the die.
Automated Navigation
Altera, an IC manufacturer, uses emission microscopes with a software tool that aligns and superimposes CAD data, layer-by-layer, on the microscope images. As a result, we can rapidly relate emissions to specific transistors, which then can be analyzed as part of the circuits in which they are used.
The company first performed backside EM in 1999. At that time, it was necessary to thin the chips under investigation to no thicker than 80 microns. At that thickness, we could obtain a sufficiently revealing optical image of chip features through the silicon to identify circuit elements related to emission sites.
Unfortunately, thinning the backside to that extent made chips vulnerable during subsequent physical analyses. Destroying a chip before its problems are adequately diagnosed obviously is unacceptable.
In early 2000, Altera began working with Hypervision and Knights Technology to port Knights’ CAD navigation software, named Merlin’s Framework, to Hypervision’s BEAMS V2000 and BEAMS V6000 Emission Microscopes. We had used the software with other inspection tools to relate front-side images to layout and schematic data. As a result, in that previous work, we confined physical inspections by focused ion beam and other invasive equipment to the smallest regions possible, speeding up determination of the root cause and minimizing damage to the die.
By April 2000, we were using the software with our backside emission microscope and, after some experimentation, determined we could thin the die in packages to 100 microns—25% thicker than was formerly practical—yet precisely resolve the physical and virtual locations of emissions.
The emission microscopes use 1,317 × 1,035 charge-coupled device arrays and a 12-bit controller that runs the imaging software. An associated computer-aided mill (CAM) back-grinds through the package and die substrate at an accuracy to within 5 microns, leaving wire bonds, bumps, and package leads intact. After emission imaging, the CAD navigation software imports layout, netlist, and schematic data from design-verification systems and cross-maps the data to the backside die images (Figures 1 and 2).
To match the imported CAD data to the optical images from the die milled to 100 microns, which have lower contrast than do images captured through thinner silicon, we anchor layout data from the netlist to such major features in the optical image as corners of metal lines or repeating structures. With the CAD data cued to the emission image, it is easy to display polysilicon layers and match them to areas of emission.
Investigative Procedures
Emission spots are not necessarily failure locations but merely may be symptoms of failures elsewhere in a circuit. So from the emission-microscope images referenced to the schematic, not only can we tell when specific transistors are behaving abnormally, but we also can diagnose failures that arise from shorts or opens in the interconnect.
We cannot directly see the short, but if it results in a transistor remaining continuously on, that is detectable. As always, successful failure analysis is the result of persistent detective work, and the better integrated the tools, the easier the task of developing random clues into an intelligible picture.
In practice, the first step is to create the window in the sample. We input values for package thickness and die length, width, and thickness into CAM, Hypervision’s Chip UnZip Tool, which creates the window and polishes the backside of the die. Next, we put the sample into the emission microscope and apply test vectors.
Naturally, we simply do not assume that just because a transistor produces an emission spot that it has a problem. We use the layout and schematic to analyze what could have gone wrong to create unexpected emissions from that transistor.
We emphasize that a thorough methodology for evaluating different scenarios is essential to diagnose the origins of failures. For example, in the past, we saw latch-up problems caused by unresolved bus contention and probably would have identified the culprit more quickly if we had both EM and a methodology that went deeply into the possible causes of anomalous emissions.
Conclusion
Trends in IC manufacturing and packaging are driving EM for failure analysis to the backside of the die. To image features in the active area of the chip through the backside, much of the substrate must be removed.
Though the package provides some mechanical support for the die, the less material removed, the better. By coordinating our emission microscopes with CAD navigation software, we automatically tie images of die under investigation to their layout, netlist, and schematic data and reduce the amount of material that must be removed from the packaged chips.
Not every problem succumbs to EM, which is why we also use other complementary tools, such as infrared analysis, to find instances of high supply currents.
About the Author
Vijay Chowdhury, a device-engineering manager, heads the failure-analysis group at Altera. She received a Ph.D. in chemistry from the University of Salford in England, and since 1986, has been working as a failure analysis manager. Altera, 101 Innovation Dr., MS4204, San Jose, CA 95134, 408-544-7442, e-mail: [email protected]
Failure Analysis by Emission Microscopy
EM allows circuit analysis with power and signal applied to either wafers or packaged chips. It works because the electron-hole recombination that takes place in a number of different semiconductor failure modes generates photons in ways that result in optical signatures. In backside EM, these can be observed through a thinned area of the substrate.
For example, consider latch-up. Latch-up accompanies forward biasing of parasitic bipolar and SCR structures inadvertently created in CMOS circuits because of fab problems, such as overlap of implant fields, or electrostatic discharge damage.
When electrons and holes recombine within these forward-biased parasitic bipolar structures, the energy they release is emitted as photons. In the case of latch-up, photons generally are emitted over a large area. The higher the bias current, the more intense the emissions. It even is possible to spot the locations of parasitic structures before latch-up occurs.
In contrast to the broad-area signature associated with latch-up, junctions undergoing avalanche breakdown, where pn junctions are subjected to excessive reverse-bias voltages, have a different signature. In this case, hot electrons create new electron-hole pairs only when they collide with Si-Si bonds in the lattice, so photons are emitted more narrowly, generally only from the junction itself.
EM is not limited to parasitic structures, however. In MOSFETs, when the drain or source is connected to the substrate, any voltage applied to the gate will drop across the gate oxide. In n-devices, an inversion layer of electrons will form at the oxide/silicon interface, creating localized electron trapping.
Electrons in the silicon within this region are raised above their ground state and conduct from the silicon into the oxide via Fowler-Nordheim tunneling. Then these already energetic electrons are boosted to higher states by the electric field across the gate oxide. Ultimately, in the polysilicon layer above the gate, these electrons may combine with holes or create new electron-hole pairs. As the electrons and holes combine, they too emit photons.
These emissions can be viewed with an emission microscope and used to detect gate-oxide defects. That is, an intact gate will emit more or less uniformly, but a damaged gate will emit less light in the damaged area.
In yet another scenario, when a deep-submicron MOSFET is biased to pinch-off (no carriers in the channel), any additional voltage applied between the gate and the drain results in an intense electric field that generates a continuous hot-carrier current between the gate and the substrate. Still higher bias voltages can result in collisions of high-energy hot electrons, which, in turn, create more electron-hole pairs.
In n-channel devices, these new electrons are swept to the drain, and the resulting electric field forces the holes to move to the source and substrate. The holes that find their way to the source then can forward-bias the source-substrate junction, creating additional electron-hole pair generation. At some point, this results in a latch-up situation called snapback.
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July 2003