Trends in Failure Analysis Techniques

Defect correlation analysis is a new approach in IC failure analysis technology.

Proper failure analysis can provide useful and cost-saving data for companies in control of their design and manufacturing processes. In this context, we are speaking of the capability to identify the nature or class of defects present in an IC that has failed one or more production tests.

Traditionally, this process consisted of a variety of destructive and nondestructive tests to identify the location and nature of the defect and frequently was followed by an autopsy of the part for verification. This methodology is expensive and time consuming and often results in a no-trouble-found (NTF) conclusion.

Recently, there have been significant advances in the technology of IC failure analysis by nondestructive electrical means alone. The goal of this new approach to failure analysis identifies the defects, maintains a database of information about each defect, and then looks for commonalities among the defects. We call this defect correlation analysis (DCA).

To achieve this goal, it is necessary to have a very exact process of defect identification using electrical test results only. Recent experiments have demonstrated that through the use of design-for-test (DFT) structures, such as scan, it is possible to identify the class or category of most defects and isolate the location of the defect to the library cell level or to within the cells themselves.

What Can Be Done With the Information?

Before getting into the details of electrical fault isolation and what can and cannot be done using the various techniques, it is useful to understand how the information might be used. Imagine the example of a 5 million gate (about 20 million transistors) synthesized ASIC being manufactured. The failure rate is not extraordinary for such a device; the yields are in the 80% to 90% range. Still, the volumes are such that a 1% improvement in yield can amount to significant savings per year. For this reason, defect correlation studies are being conducted.

As the failing test data is returned, you can sort it with respect to similar failing responses and correlate it with logical diagnostics and optical data. From this analysis, a collection of failing devices is sent to the failure analysis lab for DCA.

As each device is analyzed, the information about the type of failure, the process being used, the library cells involved, likely defect locations within a library cell, and a myriad of other data are logged and placed into a database. In time, a profile of the most common forms of defects begins to arise.

In this case, the analysis may discover that the most common failure is a short, and it shows up frequently within the DFHCP1 and DFHCP2 models. Consequently, this analysis indicates a chronic problem in these two library cells.

Since the DCA database is not limited to just one device, additional checking shows that the same defect is present in a variety of ASICS and at a variety of locations on the die. As a result, some sort of interaction between the library model and the fabrication process for that particular cell is suspected.

Figure 1. SEM Image of a Poly-Silicon Bridging Defect¹Reprinted with permission from the authors.

The analysis also lists as suspect a short between two particular metal tracks on the M2 layer. To verify this, several devices with this type of defect are sent in for autopsy with the instructions that the likely cause is a short between two suspect metal tracks on the M2 layer of specific DFHCP1 and DFHCP2 cells. When the autopsy results are returned, they confirm a splinter short between the two suspect tracks (Figure 1).

This is as far as the DCA process can be taken. Nevertheless, knowing the nature of the defect and its association with two particular library cells, it now is possible for human ingenuity to take over and mitigate the problem.

To convert this information into a yield improvement now requires work with the process engineers and the library modelers. By fine-tuning the process, it may be possible to remove the stresses that are causing the metallization problem. And by adjusting the library layout, it is likely that future defects of this sort can be avoided.

Gathering the Appropriate Data

Failure analysis is based primarily on data from scan chains and memory bit maps (from mBIST engines). The objective is to isolate the failure to a particular defect class and a particular region of the IC.

However, the test information needed to make an accurate diagnosis is not the same as the data needed to perform a quality production test. For one thing, to minimize test times, production tests tend to maximize the number of defects covered by a single test vector. In failure analysis, the goal is to minimize the number of defects activated by a test vector.

DCA requires additional test hardware and analysis software beyond the traditional datalogging of production test. Although almost any piece of test equipment would suffice for this effort, correlation analysis is based primarily on structural test techniques like scan, IDDQ, and BIST and optical methodologies such as SEM. For example, with a low-cost test system such as the Teseda V520 and an automatic test pattern generation (ATPG) tool like the Synopsys Tetramax, you have the ability to improve the yield of some critical processes.

Using the failure analysis test equipment and the analysis software, additional vectors aimed at isolating the defect must be applied. The goal of the new test set is to minimize the amount of circuitry being scrutinized for the defect.

Using the theory that a defect must lie along a sensitized path leading from a failed output back to one or more inputs, an engineer might constrain the ATPG to produce several tests sensitizing different paths with certain subpaths in common. An example of such a test could be an n-detect of a suspected stuck-at fault or even a transition fault. The results of such a test are better resolution in logic diagnostics.

Additionally, it is frequently useful to correlate I_DDQ data with the results of other tests. While there is a great deal of speculation about the value of I_DDQ as a general-purpose test tool, few would quarrel with its value as a tool in defect isolation.

For example, a path analysis might result in a number of nets being indicted as possible sources of the defect. If a short is suspected as the defect class, then the potential bridges can be enumerated using the layout information.

Once done, each potential bridge defect can be activated one at a time and an IDDQ test performed to look for the indicative current spike when the defect is activated. As a result, a scan-based test and an IDDQ test can be cross-correlated to isolate the problem to a specific locale (see sidebar).

What Defects Are We Talking About?

DCA is not intended as a process control mechanism. Short-term process control is the responsibility of the fab and can be adequately maintained by other mechanisms.

DCA is a statistical quality-control methodology that targets longer-term trends, analyzing the processes and designs and looking for ways in which both might be changed to produce higher yields. For this reason, defects are examined by categories rather than specific causes. For example, a resistive via, a stress-cracked metal track, and a missing poly interconnect would all be classified as opens. A metal splinter, an under-etched poly layer, and a metal filament would all be bridges.

Although most defects probably occur in the large number of interconnect metal layers and their associated vias and exist outside of the library cells, there is a distinct advantage in having access to the library cell circuitry and layout information. If this information is available, it is important that it be accurate.

For example, consider Figure 2, a buffer with a 4-X drive capability. The schematic shows only two transistors in the output stage, but the layout indicates that there are multiple transistors with their gates and outputs connected in parallel. If the schematic were depended on for accuracy, a possible defectï¿½an open in either the gate interconnections or the output interconnectionsï¿½would be missed.

Figure 2. Physical Layout of a 4-X Inverter Cell and Its Schematic

Nevertheless, access to the cell layout data as well as the electrical schematic provides for a more complete analysis capability and thorough defect localization capability.

An Example of Locating a Defect

How is it possible to determine the cause of a defect just from the electrical evidence? Consider the circuit in Figure 3 with four library cells, G1, G2, G3, and G4, and the interconnections between these cells.

No information concerning the layout internal to the library cells is available; nevertheless, it still is possible to infer a strong likelihood of the bridge location given that the indicated node is stuck at 0. The cause of such a failure may be attributed to a number of things including a net (metal or poly) shorted to ground, an open in the metal, and various problems with transistor fabrication.

Figure 3. A 4-Cell Circuit With Defect

By setting constraints on node G1.2 such that its state should be 1, a relatively high current will exist if the node is shorted to ground. So by correlating the IDDQ results from first applying a pattern that sets the state of net G1.2 to be 0 and then a pattern that sets the state at 1, it is possible to determine if excessive current is drawn in the 1 state. This is indirect evidence of a short on the net. (Other possibilities would have to be eliminated by further testing.) As for the location of the short, an examination of the layout will indicate those locations along the route for G1.1 where the track comes close to a ground net.

Without access to the internal layout of library element G2, it is not possible to locate the short with certainty. However, if node G1.2 is sensitized to the 0 and 1 states by a multiplicity of means (n-detect), and the evidence of a bridge exists in every case where G1.2 is in the 1 state and does not exist when it is in the 0 state, the evidence of a bridge within the interconnect track (as opposed to within the cell) is strengthened.

Future Trends

At the moment, there is no good solution for looking into the layout and circuitry of libraries and IP cores that the vendors will not make available. Certainly, the job of determining whether the defect lies within an IP core or the interconnections leading to and from the core is greatly aided by the inclusion of a wrapper surrounding the core. This could be either an IEEE P1500-compliant style of circuit or some other design as long as it is capable of adequately isolating the core from the interconnections during the test process. Further coordination with the vendor then can occur to eliminate the source of the problem.

References

1. Benware, B., Schuermyer, C., Ranganathan, S., Madge, R., Krishnamurthy, P., Tamarapalli, N., Tsai, K-H., and Rajski, J., ï¿½Impact of Multiple-Detect Test Patterns on Product Quality,ï¿½ Proceedings of the International Test Conference, 2003, pp. 1031-1040.
2. Chakravarty, S., Jain, A., Radhakrishnan, N., Savage, E.W., and Zachariah, S.T., ï¿½Experimental Evaluation of Scan Tests for Bridges,ï¿½ Proceedings of the International Test Conference, 2002, pp. 688-695.
3. Schuermyer, C., Benware, B., Cota, K., Madge, R., Daasch, R., and Ning, L., ï¿½Screening VDSM Outliers Using Nominal and Subthreshold Supply Voltage IDDQ,ï¿½ Proceedings of the International Test Conference, 2003, pp. 565-573.

About the Authors

Ken Posse is CTO at Teseda. He has 29 years of technical and business management experience at Agilent Technologies and Hewlett-Packard, where he most recently was the system architect in the Intelligent Test Solutions Division. Mr. Posse received a B.S. in aerospace engineering from the University of Michigan and an M.S. in computer engineering from the National Technological University. He is a published author, has contributed to several IEEE standards, and holds 12 patents. Teseda, 6626 Majestic Dr., Fort Collins, CO 80528, 970-223-2103, e-mail: [email protected]

Andrew Levy, director of marketing at Teseda, has more than 20 years of experience in software engineering, technical support, and marketing at Intel, Integrated Measurement Systems, Cadence, Credence Systems, Opmaxx, and Fluence. He earned a B.S. in mathematics and computer science from UCLA and an M.S. from UC Berkeley in computer science. Teseda, 315 SW Fifth Ave., Suite 11000, Portland, OR 97204, 503-223-3315, e-mail: [email protected]

Thomas W. Williams, Ph.D., is a Synopsys Fellow. Previously, Dr. Williams was with IBM Microelectronics Division as manager of the VLSI Design for Testability group. He received a B.S.E.E. from Clarkson University, an M.A. in pure mathematics from the State University of New York, and a Ph.D. in electrical engineering from Colorado State University. He is the founder or co-founder of a number of workshops and conferences dealing with testing, was named an IEEE Fellow in 1988, and received the Computer Societyï¿½s W. Wallace McDowell Award for outstanding contributions to the computer art in 1989. Synopsys, 1113 Spruce St., Boulder, CO 80302, 303-245-0493, e-mail: [email protected]

December 2004