Flavored DACs for Every Application

The digital image is identical to a real photograph. Well, try standing back a bit.

Traditional analog man-machine interfaces disappeared years ago. First, knobs were replaced by push buttons. Then came the hand-held controller, now ubiquitous and driving everything from air conditioners and microwave ovens to music centers and blenders. More recently, controls that look like knobs have reappeared. In reality, they simply are finger grips that make it easier for human operators to turn digital shaft encoders.

For sure, there is an unstoppable digital conspiracy taking place. It can be argued that our basic physiology hasnï¿½t changed in response to the digital onslaught. Our senses still operate over the same ranges they have for millennia and respond best to analog inputs. But the complacency of this position only confirms the success of the ersatz-analog-interface marketing effort. We are living in a pixilated, digitized, interpolated, and decimated universe without realizing it.

Making possible new analog-like interfaces are modern conversion devices, both analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). Precisely because humans havenï¿½t evolved to enjoy 8-b digitized sound, for example, digital audio required at least 16-b resolution to be successful. Low-cost, extremely precise, and relatively fast DACs only became practical with advanced semiconductor processes. A similar claim could be made for the high-resolution, high-speed converters used in modern communications systems.

Of course, DACs have been used for decades in test and measurement and control systems. Often, 8-b or 12-b resolution has been adequate, although in the last few years 16-b devices have replaced many 12-b solutions. Several types of architectures have been developed to meet different application requirements. In addition, a family of performance metrics has become standardized within the industry so that comparing devices is relatively straightforward.

DACs and Metrics¹
String DAC
The easiest-to-understand architecture is based on a Kelvin divider. As shown in Figure 1, the output voltage is selected from the taps on a long string of equal-value resistors. Also called a string DAC, this structure has the advantage of guaranteed monotonicity. Even if one resistor were to have zero value, progressing from the bottom to the top of the divider string, the output voltage would never decrease. Monotonic means that an output level will never decrease for increasing input codes.

Figure 1. String DAC
Courtesy of Analog Devices

Ideally, all the resistors have exactly the same value, so one output step will be identical in size to any other. Although not perfect, actual string DACs obtain very good resistor matching, so specifying a low differential nonlinearity (DNL) value is easy. DNL describes the worst-case ratio of step sizes.

For example, if 128 10-? resistors made up a string DAC driven from a 12.8-V reference, each step would be 10 mV. If one resistor were 5 ? and another 15 ?, the steps associated with them would be 5 mV and 15 mV, respectively. Considering either step, the DAC would have a DNL of ï¿½ least significant bit (LSB): the smallest step size is ï¿½ LSB, but the largest is 1ï¿½ LSB.

Itï¿½s common to use binary codes to represent DAC values. Typically, the left-most bit is the most significant bit (MSB) and the right-most the LSB. Although a so-called thermometer code might be developed internally to select the 127 output values of the 12.8-V string DAC example, externally the device would be addressed by a 7-b binary code.

If the resistors in the lower half of the string were a few percent higher than 10 ? and the ones in the upper half a few percent lower, the overall resistance might be in spec and the DNL very good. However, relative to the ideal 6.4-V value at the center of the string, the actual output could have a considerable error. This deviation from the ideal overall straight-line transfer function is termed integral nonlinearity (INL).

In addition to INL and DNL, DACs are characterized as having gain and offset errors. Offset is defined as the output corresponding to zero input code. With the offset set to zero, gain describes the slope of the transfer function. INL should be measured with any offset and gain errors removed.

Binary-Weighted DAC
In Figure 2, a very small DAC implementation is shown. Because the resistor values have a binary weighting, selecting them in all possible combinations results in 16 output values. The resistors are acting as current sources because they are summed at an op-amp summing junctionï¿½a virtual ground. Real current sources could be combined to create a voltage across an output load resistance.

Figure 2. Binary-Weighted DACCourtesy of Philips Semiconductors

R-2R DAC
An R-2R DAC can have several forms. The one shown in Figure 3 uses identical current sources to drive a resistor network that provides a voltage output. The R-2R network develops an output voltage with a 2R source impedance. A constant output impedance is important in many applications and much easier to work with than the variable output impedance of a string DAC. In addition, semiconductor processes are more amenable to accurately creating several equal current sources than sources varying by 100:1 or more in value.

Figure 3. R-2R DACCourtesy of Analog Devices

Other R-2R topologies include voltage-driven variants that sum currents from the resistor network in an op amp. It also is possible to configure the resistor network to provide a direct voltage output although this design requires a low-impedance reference voltage.

Segmented DAC
Practical high-speed DACs mix these different approaches to produce an optimum solution. For example, the Analog Devices AD9772 TxDAC is a 14-b part comprising three sections: a binary-weighted DAC forming the lowest five bits, a fully decoded section representing bits 6 to 9 providing 15 current sources each with a 32-LSB value, and a fully decoded section of 31 current sources each with a value of 512 LSBs corresponding to bits 10 to 14.

This segmented architecture uses matched currents for the MSBs where accuracy is most important. Current sources are convenient elements in DACs because differential transistor switching, so-called current steering, operates well at high speed and minimizes switching transients. The current source itself is never interrupted or disturbed in its operation. Its output simply is switched to ground or into the output summing point.

Interpolating DAC
Consideration must be given to aliasing when using a DAC. For example, updating a DAC at 30 MHz to develop a 10-MHz sine wave also creates an image signal at 20 MHz. Removing the image frequency requires a filter that does not attenuate significantly at 10 MHz but greatly does so at 20 MHz. To achieve a 60-dB stop-band rejection in only 10 MHz takes an expensive 10-pole filter.

Interpolation can be used to increase the effective update rate. In one implementation, each input data word is followed by an inserted zero, the resulting double-rate data operated on by an interpolating digital filter, and the output used to drive the DAC stages. With a 60-MHz sample rate, the image of the 10-MHz output signal occurs at 50 MHz. The filter transition region now can occupy a 40-MHz band, resulting in a much lower cost and more practical four-pole filter.

Sigma-Delta DAC
Sigma-delta DACs take interpolation to an extreme factor, oversampling by ï¿½64 or ï¿½256, for example. The interpolating filter is followed by a digital sigma-delta modulator.

The filterï¿½s input digital value represents a fraction of full scale. The function of the interpolating filter and modulator is to produce a serial output bit stream with an average density of 1s equal to the input fraction of full scale. In other words, for an input of 1000000, the modulator following a ï¿½256 oversampling filter will output a stream of alternating 1s and 0s. The average value is 0.5.

As another example, consider the input word 0000011 corresponding to 3/256. In this case, the output bit stream would consist of a 1 followed by 84 0s, another 1 followed by 85 0s, and the third 1 followed by 84 0s. The sum is equal to 256: 1 + 84 + 1 + 85 + 1 + 84 = 256. This pattern will repeat for each DAC clock cycle that the input code remains the same.

A 1-b DAC outputs very accurate analog voltages in response to a digital 1 or 0 on its input, for example +1 V and -1 V, respectively. When a 1-b DAC is driven by a bit stream, the average value of its output represents the same fraction of analog full scale as the fraction of digital full scale corresponding to the bit stream density of 1s. Low-pass filtering the DAC output produces a monotonic analog output.

The very latest sigma-delta DACs use multilevel DACs instead of a single-bit DAC. These devices provide lower noise levels and can operate faster than sigma-delta ICs that use a 1-b DAC internally.

Variations on a Theme
How well a DAC produces its analog output can be described by metrics such as the signal-to-noise ratio (SNR) and the spurious-free-dynamic-range (SFDR). A DACï¿½s output spectrum may be affected by a large number of factors including switching spikes, noise from high-value internal resistors, and code-specific inaccuracies.

In high-resolution DACs, code-related effects often stem from mismatched current sources. For example, in the Analog Devices AD9772 TxDAC, the five MSBs drive 31 equal current sources. Each source has a value of 512 LSBs, so for the converter to have no more than ï¿½ LSB DNL, these sources must be matched to better than one part in 1,024ï¿½or about 0.1%.

To reduce noise levels and spurious power beyond what can be accomplished by static matching, many manufacturers have developed dynamic element matching (DEM) procedures. For example, the British digital audio DAC manufacturer ARCAM used a proprietary algorithm to continuously vary the number and positions of the selected current sources from sample to sample.

This technique was based on work originally done by Data Conversion Systems in Cambridge, UK, hence the dCS Ring DAC nomenclature. ï¿½[The algorithm] ensures that the inevitable slight variations in the values of the current sources are randomly distributed throughout the quantizing range. This effectively turns any tolerance errors into a random white noise signal, which is far more benign than the distortion products that otherwise would have occurred. Finally, fourth-order noise shaping is used to move the bulk of the random noise up into the higher frequency spectrum above 100 kHz where it is easily removed with analog filtering.ï¿½²

DAC Use
Several types of DACs are built into DAC PC boards. Of course, there are many ways to generate a variable analog voltage and not all can be included here. For example, schemes based on pulse-width modulation often are used to develop DC voltages.

In choosing a DAC, both system and device characteristics must be considered. For example, as the sidebar discusses, sometimes the application calls for very low-level control of the circuit blocks within a multifunction DAC. Unless you can satisfy these requirements, the deviceï¿½s SFDR or even its resolution is not important.

In a PCB example, Rick Lamanna, vice president of engineering at Measurement Computing, compared the benefits of the companyï¿½s PCI-DAC6702 Multiplexed DAC Board and the PCI-DDA08/16 Board with a separate DAC per output. The PCI-DAC6702 uses multiple sample-and-hold circuits and provides eight channels of 16-b analog outputs from a single R-2R DAC. The PCI-DDA08/16 with a separate MAX542A DAC per channel has greater accuracy and less switching noise. Its price is about twice that of the multiplexed board.

According to Mr. Lamanna, ï¿½For both of these boards, a significant feature that improves perfo

rmance is autocalibration. The circuit uses separate trim DACs to adjust gain and offset. Calibration takes only minutes and guarantees 16-b monotonicity as well as maximum accuracy.ï¿½

FOR MORE INFORMATION

Calibration also was important to Dennis Kraplin, hardware engineering manager at UEI. He stressed the need for accurate calibration and the large amount of external circuitry usually required to accomplish it. However, a new series of DACs with internal digital calibration registers can achieve accurate offset and gain adjustment without the added cost of external parts. For example, the Analog Devices AD5764 quad 16-b part features adjustment of offset with 1/8-LSB resolution over a range of -16, +15.875 LSBs and gain over the range of -32 to +31 LSBs to within 1 LSB.

Isolation, required in many industrial control applications, characterizes boards from both Advantech and Data Translation. Advantechï¿½s PCI-1724U is isolated to 1,500 V and features 32 14-b analog output channels capable of a -10 to +10-V range or 0 to 20-mA and 4 to 20-mA current ranges. Also isolated, but to 500 VDC, the Data Translation Model DT9834 Module features four 16-b deglitched DACs running at up to 500 kHz per channel. The unit communicates via USB 2.

ADLINKï¿½s Hank Lin, a field applications engineer, stressed the improved performance that better voltage references have made possible in recent products. The PCI-6308V 12-b Analog Output Board previously had a DAC4814 DAC with an internal buried-zener reference. Although the device performed well, new versions of the board use an AD7564 with an adjustable ref102-based DC reference voltage. The advantages of an adjustable reference are better linearity and decreased distortion.

Very fast DACs require special design techniques of their own. Some of the technology supporting the 1.2-GS/s sampling rate in Analog Devicesï¿½ 14-b AD9736 DAC was described by James Caffrey, the companyï¿½s marketing manager for precision converters. ï¿½A low-voltage differential signaling (LVDS) data interface is used because CMOS interfaces wonï¿½t operate at this rate. In addition, internal synchronization blocks and digital controllers ensure that data is properly latched at key interfaces within the device.

ï¿½First,ï¿½ he explained, ï¿½an LVDS controller monitors the eye opening of the incoming data and adjusts the sampling point to be in the center of the eye. Next, a synchronization controller manages the handoff of data from the data clock domain to the DAC clock domain.ï¿½

Vendors often distinguish among analog output boards with waveform capability and those without. The CyberResearch Model CMFS 0240DA Two-Channel Board combines 40-MS/s 12-b waveform generation with DSP coprocessing and a 16-MB FIFO memory. National Instruments uses sigma-delta DACs in the companyï¿½s line of dynamic signal-generation boards. Because of the reduced anti-alias filtering requirements resulting from a sigma-delta DACï¿½s high oversampling ratio, these devices are well suited for generating audio signals.

Sigma-delta DACs also were the subject of comments by Tom Lawson, president of Lawson Labs. ï¿½Sigma-delta DACs offer less ripple and more bandwidth than duty-cycle modulation DACs and better linearity than R-2R DACs. A simple duty-cycle modulation DAC uses a single digital output pin that, over a fixed period of time, spends some portion of the time at the high state and the rest at the low state.ï¿½

Summary
The envelope of DAC board specifications extends up to 24-b resolution, 1.2-GS/s or higher sampling rate, and from two to 32 or more channels. Devices may include onboard voltage references, output op amps with selectable gain and offset, and even a number of synthesizer building blocks as presented in the sidebar.

Several criteria to consider in the choice of a DAC device or board were discussed by Dean Cawthon at Scientific Solutions. ï¿½We look for a DAC with high speed and good linearity that also accommodates the required analog output voltage range. Four main criteria are accuracy, speed, power, and output range.

ï¿½A parallel data DAC is generally preferred for faster data update speed. With high-speed applications,ï¿½ he continued, ï¿½you also have to worry about glitch errors produced when the DAC switches from one code to another. A DAC with an internal deglitcher to reduce the energy to below 2 nVï¿½s is a plus in instrumentation applications.

ï¿½Typically, an external voltage reference can improve upon the DACï¿½s internal reference accuracy and temperature drift. Also, autocalibration is important because it removes offset and gain errors of the DAC and, for board products, of the external op amp.ï¿½

His concluding comments give some idea of the lengths you must go to if the lowest noise and drift performance are needed. ï¿½Our LabMaster Pro optionally uses optical coupling of the DAC data to avoid analog/digital ground noise problems. We also use internal scaling resistors to set the DAC’s output range. Because they are on the same silicon substrate as other DAC circuitry, they track thermally. In some cases, you can make do with an external resistor network if only the resistor ratios are important.ï¿½

To be sure, DAC boards with easy-to-use control software are a great help to measurement system integrators. However, as with any high-precision analog circuits, obtaining the last tenth of a decibel specified by the manufacturer requires design skills and experience.

References
1. Kester, W. and Bryant, J., DACs for DSP Applications, Section 4, DAC Structures, Analog Devices, www.analog.com/Analog_Root/static/pdf/dataConverters/MixedSignal_Sect4.pdf
2. The Technology Behind the Alpha 9 CD Player, an Arcam Technical Report, 1998, www.aslgroup.com/arcam/alpha9cdtechpaper.pdf

Control of High-Speed Interpolating DACs

by Scott Hames, Director of Product Management, Interactive Circuits and Systems

Software-defined radio (SDR) transmission techniques typically involve synthesis of signals at IF or even RF frequencies. To alleviate the problems associated with streaming data at gigahertz rates and further integrate SDR systems, DAC manufacturers offer parts with on-chip clock multipliers, direct digital synthesis (DDS) numerically controlled oscillators (NCOs), interpolating filters, and mixers.

Ideally, by performing the final upconversion digitally on the DAC chip, you only need supply data at the baseband rate. Theoretically, the programmable NCO can bring substantial flexibility to the hardware, allowing spread-spectrum techniques such as frequency hopping to be software controlled.

In phase-sensitive applications such as phased array radar, exact synchronization of multiple DAC outputs is required across multiple trigger events. Separate, fast DACs previously used allowed control of the clock and data inputs, and you could ensure that the clocks and data streams were in sync.

As DAC conversion rates increased beyond 300 MHz, interpolating or digital-upconverter DACs became attractive because they accept data at the baseband rate and perform digital upconversion (DUC) on the chip before generating the analog output. Unfortunately, in most cases, you have limited ability to precisely control the internal DUC functions of these parts.

In one application, an interpolating DAC was operating as a quadrature upconverter that relied on an internal DDS NCO. The phase of any signal generated at the DAC output depended on the phase of the baseband data and the phase of the DDS NCO. Unfortunately, the NCO was free running after the chip was released from the reset condition. Its phase could not be separately controlled. For this application, we needed a register in the chip to control the starting phase of the DDS NCO and an NCO_SYNC pin on the device that would clear the phase accumulator and allow arbitrary synchronization based on an external event.

Interpolation counters and FIR/IIR/CIC filter pipelines also affect the phase of the signal. The state of the interpolation counter determines when new data is accepted into the pipeline. Unless it can be controlled based on external conditions, phase uncertainty exists. And if old, invalid data is not flushed from filter pipelines, it could corrupt the new input.

Because most interpolating DACs do not allow precise external synchronization of important operations in the signal-processing chain, they may not be suitable for phase-sensitive applications. However, there are DUC ASICs available, such as the GrayChip GC4116 and GC5016, that provide this capability (Figure 4).

Figure 4. Typical DUC Block Diagram

These devices do require discrete high-speed DACs to do the final digital-to-analog conversion, but these components are readily available. The caveat is that they put responsibility for proper control of the device squarely on the system designer or application programmer. The learning curve may be substantial, but in the hands of an experienced user, these devices are very powerful.

November 2005