Small Instruments With Big Performance

Logic analyzers (LAs) are used to examine the simultaneous relationships among several digital signals. Both timing and state operating modes may be available on the same instrument. A state analyzer uses a clock provided by the DUT to acquire data. The clock is positioned relative to data transitions so only stable, settled data states are recorded.

In contrast, a timing analyzer uses a totally independent asynchronous clock generated internally by the LA. All incoming signals are simultaneously sampled by this clock, which typically runs at a much higher rate than the DUT logic being examined.

A timing analyzer helps you prove that one signal changed a certain amount of time before another or that several signals all changed within some very small amount of time. State analyzers are used to track the various combinations of logic levels that existed among the channels. Whether one channel changed a nanosecond before or after another channel isn't relevant in a 100-MS/s state analyzer. It is relevant in a timing analyzer.

In both state and timing modes, sophisticated triggering helps you describe and capture only certain events. Large capture memories ensure that you can see events leading up to the trigger condition as well as subsequent events. The assumption is that you can determine why a system is behaving incorrectly or at least get valuable clues by examining conditions ahead of and after the trigger.

Modern LAs have built-in features to help in this examination process. You can set up a very detailed if-then-else trigger tree to accurately pinpoint erroneous events so that the errant byte or bytes quickly are found. Inevitably, given that you don't initially know what you are looking for, troubleshooting generally takes some time even with the best triggering systems.

Not surprisingly, this LA capability has become complex and includes multiple levels of programmable conditions. For example, the DigiView™ Model DV3400 has eight universal trigger match circuits and four configurable four-stage trigger sequencers. A trigger match circuit compares the incoming channel data to a predefined type and state.

For the DV3400, the available match types include pattern, edges, stable, equal, not equal, greater than, greater than or equal, less than, and less than or equal. After selecting the type of match, you enter a combination of 0, 1, and X (don't care) across all 18 or 36 channels.

As shown in Figure 1, the outputs of the eight match circuits then are combined and applied to a succession of sequencers. In the example shown, when stable states corresponding to the programmed values are present, outputs from match circuits 2 and 3 are combined via terms 2 and 3 and applied to the counters in sequencer 1. Match 2 conditions must be satisfied 1,024 times before term 3 is considered, and this condition must occur 64 times before sequencer 2 is enabled. The trigger is output only after all events occur the programmed number of times and in the predefined order.

Figure 1. DigiView Trigger Tree Logic
Courtesy of TechTools

Triggered data capture is a major LA attribute that relates to several low-level capabilities. According to Jerry Merrill, CEO of TechTools, source of the DigiView LAs, “Any LA, whether stand-alone or PC-based, must:
• Maintain the DUT's signal integrity.
• Accurately determine each signal's logic level relative to a threshold.
• Tolerate over/undervoltage conditions.
• Store the data samples in real time.
• Optionally, compress the data samples in real time.
• Detect trigger conditions in real time.
• Detect buffer full and halt acquisition.

“After the data has been captured, the instrument is required to present it as waveforms, tables, or lists; measure and interpret the data during analysis; enable the data to be searched and saved or restored; and optionally support e-mail, remote printing, screen captures, and data exporting. A PC-based instrument also must transfer data quickly to the PC host,” Mr. Merrill explained.

Stand-Alone vs. PC-Based

Cost and size are two obvious differences that distinguish these two forms of LAs, but so too are speed, memory length, and analysis flexibility. Often, PC-based LAs are only large enough to carry the required connectors and logic circuitry. USB-based analyzers are powered from the bus so the space usually taken by an on-board power supply is saved. In addition, many PC-based LAs integrate virtually all their functionality within a large FPGA, further minimizing the PCB space required.

If your DUT only has 32 or fewer logic lines and operates with a relatively slow clock, you may be able to use the $389 Intronix Model LA1034 LogicPort LA shown in Figure 2. It has 34 input channels so you can capture a couple of control lines as well as 32 data signals and samples asynchronously from 1 kHz to 500 MS/s and synchronously from DC to 200 MS/s.

Figure 2. LA1034 LogicPort LA
Courtesy of Intronix Test Instruments

“The LA1034's logic and memory are entirely contained within a single FPGA,” commented Harrison Young III, company CEO. “This keeps the speed up and the cost down compared with products having external memory interfaces. The LA1034's efficient lossless compression algorithm allows its buffer depth to be greatly extended with no loss in signal integrity.”

Lossless signal compression is included in this product because its basic memory depth is 2,048 S/channel. To conserve memory, the LA1034 only records data transitions.

Lossless data compression relies on redundancy within the data, which can be encoded to reduce storage requirements. The amount of compression possible depends on the nature of the data.

For example, the LA1034 datasheet quotes a 2³³:1 maximum compression ratio or a factor of greater than eight billion. This degree of compression is possible for a signal starting with a single logic 1 followed by eight billion zeros. If your signals typically consist of a few fast pulses with lots of dead time, compression can be very useful. However, for very active signals with a large number of transitions, the effective compression ratio will be small.

In the LA1034's favor, the datasheet clearly states a few key input parameters sometimes missing from low-cost LA specifications. State-mode setup and hold times refer to the length of time that the data must be settled to its final state before and after the sampling clock edge. The quoted 2.0-ns setup time and 0.0-ns hold time are consistent with 200-MS/s state sampling. Further, the 2-ns window can be adjusted ±2.5 ns, giving you much greater control of the relative position of the sampling instant.

Channel-to-Channel Skew
Also, a 0.6-ns typical skew and 1.0-ns maximum channel-to-channel skew are quoted. Few low-cost LAs deal with channel skew at all. Skew is important because it determines the degree to which displayed data timing can be believed.

If an analyzer specifies worst-case channel-to-channel skew of 1 ns, simultaneous transitions on channel A and channel B could appear to be 1 ns apart with either A or B leading the other. There could be as much as a 1-ns uncertainty between the fastest and slowest channels being sampled. There is a chance that an asynchronous sampling clock will fall during this 1-ns window depending on the relationship between the clock rate and the data rate.

If the sampling clock were derived from the DUT timing, then the sampling no longer could be considered asynchronous. A fixed relationship between the two clocks means that the LA actually would be operating with synchronous clocking.

It might be possible to arrange the phase of the sampling clock relative to that of the DUT timing so that samples never occurred during the 1-ns uncertainty period. This is an advantage of synchronous clocking for state data acquisition. Unless something goes terribly wrong, each acquisition is guaranteed to have occurred during periods when the data lines are settled and stable.

At the opposite extreme, although very unlikely, it is possible for an asynchronous sampling clock to be so closely aligned to the DUT timing that a large proportion of the samples falls during the 1-ns uncertainty period. On a DSO, this undesirable situation also is possible so these instruments deliberately offset the sampling clock phase between acquisitions to upset potential synchronism with the data. Unfortunately, if either a logic analyzer or a DSO captures only one long acquisition to memory, it could accidentally be made under nearly synchronous conditions.

Typically, near-synchronous operation doesn't occur because the data timing and asynchronous sampling clock are independent. Nevertheless, when the clock rate in this example reaches 1 GS/s, you are guaranteed to catch each 1-ns transition period.

At faster rates, more than one sample always will fall in that period. The result can be acquisition of incorrect relationships between two or more data signals. You can't extract meaningful signal-to-signal timing information beyond the instrument's inherent skew limitations.

How can you ensure that the acquired data accurately reflects what actually occurred? One way is to attach a pair of probes to the same signal and observe the displayed traces as the sampling rate is increased. At some point you will see transitions on one signal lag those on the other. Now you know which channel is slower and by approximately how much. If you are working with only a few channels, you might adjust the lengths of the probe wires to partially compensate for the timing differences, reducing the overall skew.

For a large number of channels, it may be good enough to confirm that all signal transitions are within some measurable skew, which could be considerably less than the manufacturer's guaranteed worst-case figure. At least you would know to what degree you could believe the displayed data at high sampling rates. Typically, channel delays don't change wildly with time or temperature so this type of skew calibration wouldn't have to be done often unless especially critical measurements were being made.

Despite inherent channel-to-channel timing uncertainty, very high asynchronous sampling rates really are useful because they unambiguously reveal a lot about individual signals. For example,
at a 4-GHz rate each transition is displayed within a 250-ps uncertainty of its actual occurrence. The worst-case uncertainty in the period between transitions is twice the sample period or 500 ps in this case.

The LA1034 has a maximum asynchronous sampling rate of 500 MS/s. In contrast, Acute Technology's TravelLogic Series LA features a 4-GS/s rate across 36 channels. It also has a 200-MS/s state mode maximum sampling rate (Figure 3).

Figure 3. TravelLogic LA
Courtesy of Acute Technology

The TravelLogic unit has separate high-speed and slower speed memories. For timing analysis at rates as fast as 1.6 GS/s, a large memory is multiplexed to trade speed for channels. Model TL2036 offers 4-kS memory depth across all 36 channels at 200 MS/s, increasing to 512 kS/channel in the Model TL2136 and 2 MS/channel in the Model TL2236. As the sampling rate increases from 200 to 400 MS/s, 800 MS/s, and 1.6 GS/s, the number of channels reduces from 36 to 18, 9, and 4, and the memory length increases by factors of 2, 4, 8, and 16, respectively.

However, at the 2-GS/s rate, only a 5-kS memory is available, and it is reduced to a 2.5-kS length at the highest 4-GS/s speed. This split between fast and slow memory is similar to that used in the Tektronix 5000 Series stand-alone LAs, and according to Acute Technology President C. C. Lee, the TravelLogic Series competes with some of the Tektronix 36-channel products.

Timing-Mode Sampling
Few other PC-based LAs offer such a high timing-mode sampling rate. Scott Savage, product manager, high-speed digital I/O at National Instruments (NI), said, “One of the limiting factors restricting PC-based LA development compared to that of larger stand-alone instruments is the clock rate of digital pin electronics. Stand-alone instruments offer timing-mode sampling rates greater than 4 GS/s. Commercial off-the-shelf single-ended technology is limited to about 400 Mb/s, making it very difficult to exceed this rate with a PC-based instrument.

“Probing and connectivity also pose challenges with impedance matching and reflections at higher speeds,” he continued. “Most stand-alone instrument companies offer very advanced probing options to complement their LAs at high speeds. Since most PC-based LAs run at slower speeds, it's typically an area of less investment.”

All NI instruments are PC-based, including the Model PXI-6542/52 100-MHz Digital I/O module that can be used as an LA. Gradually, as FPGAs have become more powerful, virtual instruments have become faster. For example, the on-board FPGA in the NI PXI-655x products implements real-time bit comparison of acquired data vs. expected data on a per-channel, per-cycle basis (Figure 4).

Figure 4. PXI-6552 Digital I/O Module
Courtesy of National Instruments

Mr. Savage's comments about high-speed reflections and impedance matching relate to the data signals themselves and not to the asynchronous sampling clock. Signal fidelity is determined by the input channel bandwidth, which results from a combination of the probe, connecting cable, and LA input characteristics and often is not directly specified.

A stand-alone LA may work with a much narrower data pulse than a PC-based LA, indicating a greater input bandwidth. For example, the Tektronix TLA7NAx LA Module works with 450-Mb/s state-mode data rates. The latest Agilent Technologies Model 16760A Timing and State Module for the 16900A LA supports up to 800-Mb/s state-mode acquisition. A PC-based LA generally has a maximum state-mode rate of 200 MS/s.

The numbers by themselves don't tell the entire story. High-speed data inputs must be treated correctly to maintain signal integrity. Most PC-based LAs provide simple wire connections to the DUT. This technology is limited to about 100-MHz bandwidth data. Higher frequency content that exists in very fast edges will cause reflections that can distort signal timing as well as amplitude.

Signals in simple wire probes propagate at about 8″/ns, which means that the input signal following a 4″ wire connection will lag the actual DUT signal by 0.5 ns. Because the DUT output and LA input impedances are not matched to each other or to the wire probe impedance, a fast signal transition will be reflected back to the DUT, from there back to the input, and so on. A succession of reflections takes place at 1-ns intervals, but damping quickly causes the amplitude to reduce below the input threshold.

You may record one of these reflections when using a very high asynchronous sampling rate, although most PC-based LAs don't support a sufficiently high bandwidth to capture reflections. This is not the case for stand-alone LAs that use proprietary probing solutions specifically designed to maintain signal integrity and minimize reflections.

Memory Depth
Several PC-based LAs have small memories and rely on data compression to extend the effective memory size. For example, the 34-channel GAO Tek Model LA5034 and Intronix Model LA1034 are similar in offering 2 kS/channel. Longer memories are available, such as 512 kS/channel in the DigiView Model DV3400 and Link Instruments LA-5000 Series. And the TravelLogic Model TL2236 offers 2 MS/channel.

Nevertheless, as NI's Mr. Savage pointed out, some PC-based LAs can capture and store digital signals to disk for detailed post-acquisition analysis. “A high-capacity storage device such as a RAID array can hold terabytes of information, and with the high bandwidth PCI Express or PXI Express buses, engineers can record data at rates previously impossible in a test system. NI data acquisition solutions can transfer data up to 600 MB/s. The combination of very fast data rate and very large storage capacity is not found in stand-alone instruments,” he said.

Summary

Just as real estate ads emphasize location, location, location, high-speed digital data acquisition is all about bandwidth, bandwidth, bandwidth. If you must determine that two or more signals change state within a short time of each other, you probably need a stand-alone LA. A very fast asynchronous sampling rate may not be sufficient unless the input channels accurately handle fast edge rates.

However, if you can work within the speed limitations of a PC-based LA, you may find a low-cost instrument suits your needs. Sophisticated triggering is complemented in many cases by serial bus decode capabilities. For example, the Intronix LA1034 comes with analysis software including interpreters for I²C, SPI, RS-232, and PS/2 serial buses. The interpreted values are displayed directly within the waveforms, giving you a precise indication of when and how the values were derived.

There are several variations on the LA theme. For example, Finisar's Bus Doctor is a PC-based protocol analyzer that also functions as an LA. The instrument features up to 256-M event memory and has the benefit of simultaneous protocol and logic analysis. You can capture bus traffic as well as logic transitions in multiprotocol systems. Data is acquired at rates up to 250 MS/s.

In addition, some PC-based LAs offer data generation as well as capture. Link Instruments' LA-5000 supports a maximum of 160 channels through up to five 32-channel pods. As Todd Schreibman, the company's sales manager, explained, “Each bank of channels can be configured as a pattern generator or an LA and can be set to a unique threshold level to accommodate a specific logic family. The pattern software generates bus signals for a wide variety of protocols and widths from I²C and SPI to complex 32-b buses with multiplexed address/data signals. A powerful design tool helps create bus signals, or you can capture actual waveforms and play them back to simulate an FPGA.”

A tempting feature of some PC-based LAs is the user's ability to modify presentation of the data or even to create custom analysis routines. Of course, doing so implies a learning curve as well as a willingness to be responsible for any analysis errors that a new routine might produce. Nevertheless, all PC-based LAs have the benefit of nearly universal connectivity and unlimited data archiving, two things stand-alone instruments often lack.

With so many capabilities available at attractive prices, you need to have a clear idea of your basic requirements. As well as being within a budget limit, an LA must have sufficient channels for all the signals that need to be simultaneously examined. The channel and clock speeds for state and timing capture have to be fast enough to deal with your data rates and provide the desired timing resolution. And, to ensure that you can identify problems quickly, a range of trigger capabilities is important.